# MSP430FR2673TRHBR

**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · HVQFN-32-EP(5x5)

MSP430FR2673TRHBR from Texas Instruments, in a HVQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RST/NMI/SBWTDIO | bidirectional | Reset input (internal pullup enabled after BOR), NMI input, or Spy-Bi-Wire data I/O, powered from DVCC. |
| 2 | TEST/SBWTCK | input | Test mode input with internal pulldown always enabled, also Spy-Bi-Wire clock input; leave open if unused. |
| 3 | P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+ | bidirectional | General-purpose I/O multiplexed with eUSCI_A0 UART TXD/SPI SIMO, TA1.2, JTAG TCK, ADC input A4 and VREF+ output. |
| 4 | P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5 | bidirectional | General-purpose I/O multiplexed with eUSCI_A0 UART RXD/SPI SOMI, TA1.1, JTAG TMS and ADC input A5. |
| 5 | P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6 | bidirectional | General-purpose I/O multiplexed with eUSCI_A0 clock, TA1 clock input, JTAG TDI/TCLK and ADC input A6. |
| 6 | P1.7/UCA0STE/SMCLK/TDO/A7 | bidirectional | General-purpose I/O multiplexed with eUSCI_A0 STE, SMCLK output, JTAG TDO and ADC input A7. |
| 7 | P1.0/UCB0STE/TA0CLK/A0/Veref+ | bidirectional | General-purpose I/O multiplexed with eUSCI_B0 STE, TA0 clock input, ADC input A0 and ADC positive reference Veref+. |
| 8 | P1.1/UCB0CLK/TA0.1/COMP0.0/A1 | bidirectional | General-purpose I/O multiplexed with eUSCI_B0 clock, TA0.1, eCOMP0 input C0 and ADC input A1. |
| 9 | P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref- | bidirectional | General-purpose I/O multiplexed with eUSCI_B0 SIMO/SDA, TA0.2, ADC input A2 and ADC negative reference Veref-. |
| 10 | P1.3/UCB0SOMI/UCB0SCL/MCLK/A3 | bidirectional | General-purpose I/O multiplexed with eUSCI_B0 SOMI/SCL, MCLK output and ADC input A3. |
| 11 | P2.2/SYNC/ACLK/COMP0.1 | bidirectional | General-purpose I/O multiplexed with CapTIvate synchronous trigger input, ACLK output and eCOMP0 input C1. |
| 12 | P3.0/TA2.2/CAP0.0 | bidirectional | General-purpose I/O multiplexed with TA2.2 and CapTIvate channel CAP0.0. |
| 13 | P3.3/TA2.1/CAP0.1 | bidirectional | General-purpose I/O multiplexed with TA2.1 and CapTIvate channel CAP0.1. |
| 14 | P2.3/TA2.0/CAP0.2 | bidirectional | General-purpose I/O multiplexed with TA2.0 and CapTIvate channel CAP0.2. |
| 15 | P3.4/TA2CLK/COMP0OUT/CAP0.3 | bidirectional | General-purpose I/O multiplexed with TA2 clock input, eCOMP0 output and CapTIvate channel CAP0.3. |
| 16 | P3.1/UCA1STE/CAP1.0 | bidirectional | General-purpose I/O multiplexed with eUSCI_A1 STE and CapTIvate channel CAP1.0. |
| 17 | P2.4/UCA1CLK/CAP1.1 | bidirectional | General-purpose I/O multiplexed with eUSCI_A1 clock and CapTIvate channel CAP1.1. |
| 18 | P2.5/UCA1RXD/UCA1SOMI/CAP1.2 | bidirectional | General-purpose I/O multiplexed with eUSCI_A1 UART RXD/SPI SOMI and CapTIvate channel CAP1.2. |
| 19 | P2.6/UCA1TXD/UCA1SIMO/CAP1.3 | bidirectional | General-purpose I/O multiplexed with eUSCI_A1 UART TXD/SPI SIMO and CapTIvate channel CAP1.3. |
| 20 | VREG | power_out | CapTIvate regulator decoupling pin; requires a 1 µF capacitor with ESR of 200 mΩ maximum. |
| 21 | P3.7/TA3.2/CAP2.0 | bidirectional | General-purpose I/O multiplexed with TA3.2 and CapTIvate channel CAP2.0. |
| 22 | P4.0/TA3.1/CAP2.1 | bidirectional | General-purpose I/O multiplexed with TA3.1 and CapTIvate channel CAP2.1. |
| 23 | P4.1/TA3.0/CAP2.2 | bidirectional | General-purpose I/O multiplexed with TA3.0 and CapTIvate channel CAP2.2. |
| 24 | P4.2/TA3CLK/CAP2.3 | bidirectional | General-purpose I/O multiplexed with TA3 clock input and CapTIvate channel CAP2.3. |
| 25 | P2.7/UCB1STE/CAP3.0 | bidirectional | General-purpose I/O multiplexed with eUSCI_B1 STE and CapTIvate channel CAP3.0. |
| 26 | P3.5/UCB1CLK/TB0TRG/CAP3.1 | bidirectional | General-purpose I/O multiplexed with eUSCI_B1 clock, Timer_B TB0 external trigger input and CapTIvate channel CAP3.1. |
| 27 | P3.2/UCB1SIMO/UCB1SDA/CAP3.2 | bidirectional | General-purpose I/O multiplexed with eUSCI_B1 SIMO/SDA and CapTIvate channel CAP3.2. |
| 28 | P3.6/UCB1SOMI/UCB1SCL/CAP3.3 | bidirectional | General-purpose I/O multiplexed with eUSCI_B1 SOMI/SCL and CapTIvate channel CAP3.3. |
| 29 | P2.0/XOUT | bidirectional | General-purpose I/O or output terminal for the 32 kHz crystal oscillator. |
| 30 | P2.1/XIN | bidirectional | General-purpose I/O or input terminal for the 32 kHz crystal oscillator or external digital clock. |
| 31 | DVSS | power_in | Digital ground supply pin, 0 V reference. |
| 32 | DVCC | power_in | Digital power supply pin, 1.8 V to 3.6 V (2.7 V to 3.6 V in DVCC electrode charge mode), with 4.7 µF to 10 µF recommended capacitor. |
| 33 | PAD | passive | VQFN exposed thermal pad; TI recommends connecting it to VSS. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HVQFN-32-EP(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 33 |

## CAD (KiCad official)

- Symbol: `MSP430FR2673TRHBR`
- Footprint: `Package_DFN_QFN:HVQFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm`
- 3D model: HVQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `msp430fr2673trhbr-etched.step` / `msp430fr2673trhbr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430fr2673trhbr.step` / `msp430fr2673trhbr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430fr2676) (123 pp, sha256 `7b85e943f4b7c4ad`, retrieved 2026-10-01, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/msp430fr2673trhbr-datasheet.pdf)