component
MSP430FR2533IRHBR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430FR2533IRHBR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-32-EP(5x5)
MSP430FR2533IRHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RST/NMI/SBWTDIO | input | Active-low reset input, nonmaskable interrupt input, or Spy-Bi-Wire data input/output |
| 2 | TEST/SBWTCK | input | JTAG test mode enable input or Spy-Bi-Wire clock input |
| 3 | P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+ | bidirectional | GPIO P1.4 with multiplex support for UART/SPI transmit, Timer TA1 capture/compare, ADC channel A4, JTAG TCK, or 1.2-V reference output |
| 4 | P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5 | bidirectional | GPIO P1.5 with multiplex support for UART/SPI receive, Timer TA1 capture/compare, ADC channel A5, or JTAG TMS |
| 5 | P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6 | bidirectional | GPIO P1.6 with multiplex support for UART/SPI clock, Timer TA1 clock input, ADC channel A6, or JTAG TDI/TCLK |
| 6 | P1.7/UCA0STE/SMCLK/TDO/A7 | bidirectional | GPIO P1.7 with multiplex support for UART/SPI slave transmit enable, SMCLK output, ADC channel A7, or JTAG TDO |
| 7 | P1.0/UCB0STE/TA0CLK/A0/Veref+ | bidirectional | GPIO P1.0 with multiplex support for I2C/SPI slave transmit enable, Timer TA0 clock input, ADC channel A0, or ADC positive reference input |
| 8 | P1.1/UCB0CLK/TA0.1/A1 | bidirectional | GPIO P1.1 with multiplex support for I2C/SPI clock, Timer TA0 capture/compare, or ADC channel A1 |
| 9 | P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref- | bidirectional | GPIO P1.2 with multiplex support for I2C data/SPI data, Timer TA0 capture/compare, ADC channel A2, or ADC negative reference input |
| 10 | P1.3/UCB0SOMI/UCB0SCL/MCLK/A3 | bidirectional | GPIO P1.3 with multiplex support for I2C clock/SPI data, MCLK output, or ADC channel A3 |
| 11 | P2.2/SYNC/ACLK | bidirectional | GPIO P2.2 with multiplex support for CapTIvate synchronous trigger input or ACLK output |
| 12 | P3.0/CAP0.0 | bidirectional | GPIO P3.0 or CapTIvate sensing channel CAP0.0 |
| 13 | CAP0.1 | bidirectional | CapTIvate sensing channel CAP0.1 |
| 14 | P2.3/CAP0.2 | bidirectional | GPIO P2.3 or CapTIvate sensing channel CAP0.2 |
| 15 | CAP0.3 | bidirectional | CapTIvate sensing channel CAP0.3 |
| 16 | P3.1/UCA1STE/CAP1.0 | bidirectional | GPIO P3.1 with multiplex support for UART/SPI slave transmit enable or CapTIvate sensing channel CAP1.0 |
| 17 | P2.4/UCA1CLK/CAP1.1 | bidirectional | GPIO P2.4 with multiplex support for UART/SPI clock or CapTIvate sensing channel CAP1.1 |
| 18 | P2.5/UCA1RXD/UCA1SOMI/CAP1.2 | bidirectional | GPIO P2.5 with multiplex support for UART/SPI receive data or CapTIvate sensing channel CAP1.2 |
| 19 | P2.6/UCA1TXD/UCA1SIMO/CAP1.3 | bidirectional | GPIO P2.6 with multiplex support for UART/SPI transmit data or CapTIvate sensing channel CAP1.3 |
| 20 | VREG | power_out | CapTIvate regulator 1.5-V regulated output for external decoupling capacitor connection (ESR ≤ 200 mΩ, 0.8-1.2 µF) |
| 21 | CAP2.0 | bidirectional | CapTIvate sensing channel CAP2.0 |
| 22 | CAP2.1 | bidirectional | CapTIvate sensing channel CAP2.1 |
| 23 | CAP2.2 | bidirectional | CapTIvate sensing channel CAP2.2 |
| 24 | CAP2.3 | bidirectional | CapTIvate sensing channel CAP2.3 |
| 25 | P2.7/CAP3.0 | bidirectional | GPIO P2.7 or CapTIvate sensing channel CAP3.0 |
| 26 | CAP3.1 | bidirectional | CapTIvate sensing channel CAP3.1 |
| 27 | P3.2/CAP3.2 | bidirectional | GPIO P3.2 or CapTIvate sensing channel CAP3.2 |
| 28 | CAP3.3 | bidirectional | CapTIvate sensing channel CAP3.3 |
| 29 | P2.0/XOUT | bidirectional | GPIO P2.0 or crystal oscillator output terminal for 32-kHz crystal with external load capacitance 3.7-12.5 pF |
| 30 | P2.1/XIN | bidirectional | GPIO P2.1 or crystal oscillator input terminal for 32-kHz crystal with external load capacitance 3.7-12.5 pF |
| 31 | DVSS | power_in | Power supply ground (0 V reference) |
| 32 | DVCC | power_in | Power supply input voltage 1.8-3.6 V with 4.7-10 µF and 100 nF bypass capacitors recommended |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32-EP(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 33 |
CAD (KiCad official)
- Symbol:
MSP430FR2533IRHBR - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
msp430fr2533irhbr-etched.step/msp430fr2533irhbr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430fr2533irhbr.step/msp430fr2533irhbr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (111 pp, sha256
99ff2112334bfba1, retrieved 2026-09-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).