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MSP430FR2476TRHBR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSP430FR2476TRHBR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-32-EP(5x5)

MSP430FR2476TRHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RST/NMI/SBWTDIO bidirectional Active-low reset input, Nonmaskable interrupt input, or Spy-Bi-Wire data I/O; configurable via SFRRPCR register with internal 47 kΩ pullup available.
2 TEST/SBWTCK input JTAG test mode enable and Spy-Bi-Wire clock input with internal 20-35 kΩ pulldown always enabled.
3 P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+ bidirectional General-purpose I/O P1.4 with configurable functions including UART/SPI/Timer_A1/JTAG; also serves as analog input A4 and positive reference voltage output (1.2 V with EXTREFEN=1).
4 P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5 bidirectional General-purpose I/O P1.5 with configurable functions for UART/SPI/Timer_A1/JTAG and analog input A5.
5 P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6 bidirectional General-purpose I/O P1.6 with configurable functions for UART/SPI clock, Timer_A1 clock, JTAG test data input, and analog input A6.
6 P1.7/UCA0STE/SMCLK/TDO/A7 bidirectional General-purpose I/O P1.7 with configurable functions for SPI slave transmit enable, subsystem master clock output, JTAG test data output, and analog input A7.
7 P1.0/UCB0STE/TA0CLK/A0/Veref+ bidirectional General-purpose I/O P1.0 with configurable functions for I2C/SPI slave transmit enable, Timer_A0 clock, analog input A0, and positive ADC reference input.
8 P1.1/UCB0CLK/TA0.1/COMP0.0/A1 bidirectional General-purpose I/O P1.1 with configurable functions for I2C/SPI clock, Timer_A0 capture/compare, enhanced comparator input C0, and analog input A1.
9 P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref- bidirectional General-purpose I/O P1.2 with configurable functions for I2C data/SPI slave-in/master-out, Timer_A0 capture/compare, analog input A2, and negative ADC reference input.
10 P1.3/UCB0SOMI/UCB0SCL/MCLK/A3 bidirectional General-purpose I/O P1.3 with configurable functions for I2C clock/SPI slave-out/master-in, main system clock output, and analog input A3.
11 P2.2/ACLK/COMP0.1 bidirectional General-purpose I/O P2.2 with auxiliary clock output and enhanced comparator input C1.
12 P3.0/TA2.2 bidirectional General-purpose I/O P3.0 with Timer_A2 CCR2 capture/compare and PWM output capability.
13 P3.3/TA2.1 bidirectional General-purpose I/O P3.3 with Timer_A2 CCR1 capture/compare and PWM output capability.
14 P2.3/TA2.0 bidirectional General-purpose I/O P2.3 with Timer_A2 CCR0 capture/compare and PWM output capability.
15 P3.4/TA2CLK/COMP0OUT bidirectional General-purpose I/O P3.4 with Timer_A2 clock input and enhanced comparator output (COUT).
16 P3.1/UCA1STE bidirectional General-purpose I/O P3.1 with UART/SPI slave transmit enable function for eUSCI_A1.
17 P2.4/UCA1CLK bidirectional General-purpose I/O P2.4 with UART/SPI clock function for eUSCI_A1.
18 P2.5/UCA1RXD/UCA1SOMI bidirectional General-purpose I/O P2.5 with UART receive data and SPI slave-out/master-in function for eUSCI_A1.
19 P2.6/UCA1TXD/UCA1SIMO bidirectional General-purpose I/O P2.6 with UART transmit data and SPI slave-in/master-out function for eUSCI_A1.
20 DNC unconnected Do not connect; reserved pin with no internal connection.
21 P3.7/TA3.2 bidirectional General-purpose I/O P3.7 with Timer_A3 CCR2 capture/compare and PWM output capability.
22 P4.0/TA3.1 bidirectional General-purpose I/O P4.0 with Timer_A3 CCR1 capture/compare and PWM output capability.
23 P4.1/TA3.0 bidirectional General-purpose I/O P4.1 with Timer_A3 CCR0 capture/compare and PWM output capability.
24 P4.2/TA3CLK bidirectional General-purpose I/O P4.2 with Timer_A3 clock input function.
25 P2.7/UCB1STE bidirectional General-purpose I/O P2.7 with I2C/SPI slave transmit enable function for eUSCI_B1.
26 P3.5/UCB1CLK/TB0TRG bidirectional General-purpose I/O P3.5 with I2C/SPI clock function for eUSCI_B1 and Timer_B0 external trigger input.
27 P3.2/UCB1SIMO/UCB1SDA bidirectional General-purpose I/O P3.2 with I2C data/SPI slave-in/master-out function for eUSCI_B1.
28 P3.6/UCB1SOMI/UCB1SCL bidirectional General-purpose I/O P3.6 with I2C clock/SPI slave-out/master-in function for eUSCI_B1.
29 P2.0/XOUT output Crystal oscillator output terminal for low-frequency 32 kHz external crystal; requires external load capacitor CL2.
30 P2.1/XIN input Crystal oscillator input terminal for low-frequency 32 kHz external crystal; requires external load capacitor CL1.
31 DVSS power_in Ground supply voltage (0 V reference); must be connected to system ground with short traces.
32 DVCC power_in Main positive supply voltage (1.8 V to 3.6 V); requires 10 µF bulk and 100 nF bypass capacitor placed close to pin.
33 PAD passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(5x5)
Category Embedded Processors & Controllers
Pins 33

CAD (KiCad official)

  • Symbol: MSP430FR2476TRHBR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: msp430fr2476trhbr-etched.step / msp430fr2476trhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430fr2476trhbr.step / msp430fr2476trhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (113 pp, sha256 8a5915ac0a845eba, retrieved 2026-09-26, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF