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MSP430FR2433IRGER
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430FR2433IRGER
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-24-EP(4x4)
MSP430FR2433IRGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RST/NMI/SBWTDIO | input | Active-low reset input, nonmaskable interrupt input, and Spy-Bi-Wire data input/output for device programming and debugging. |
| 2 | TEST/SBWTCK | input | Test mode control pin and Spy-Bi-Wire clock input for JTAG interface or Spy-Bi-Wire programming mode selection. |
| 3 | P1.4 | bidirectional | General-purpose I/O port P1.4; multiplexed with UCA0TXD (UART transmit), UCA0SIMO (SPI slave in/master out), TA1.2 (Timer A1 capture/compare), TCK (JTAG clock), ADC channel A4, and VREF+ (ADC positive reference output). |
| 4 | P1.5 | bidirectional | General-purpose I/O port P1.5; multiplexed with UCA0RXD (UART receive), UCA0SOMI (SPI slave out/master in), TA1.1 (Timer A1 capture/compare), TMS (JTAG test mode select), and ADC channel A5. |
| 5 | P1.6 | bidirectional | General-purpose I/O port P1.6; multiplexed with UCA0CLK (SPI/UART clock), TA1CLK (Timer A1 clock input), TDI (JTAG test data input), TCLK (JTAG test clock), and ADC channel A6. |
| 6 | P1.7 | bidirectional | General-purpose I/O port P1.7; multiplexed with UCA0STE (SPI slave transmit enable), SMCLK (sub-main clock output), TDO (JTAG test data output), and ADC channel A7. |
| 7 | P1.0 | bidirectional | General-purpose I/O port P1.0; multiplexed with UCB0STE (eUSCI_B0 SPI slave transmit enable), TA0CLK (Timer A0 clock input), ADC channel A0, and Veref+ (ADC positive reference input). |
| 8 | P1.1 | bidirectional | General-purpose I/O port P1.1; multiplexed with UCB0CLK (eUSCI_B0 I2C/SPI clock), TA0.1 (Timer A0 capture/compare output), and ADC channel A1. |
| 9 | P1.2 | bidirectional | General-purpose I/O port P1.2; multiplexed with UCB0SIMO (SPI slave in/master out), UCB0SDA (I2C data), TA0.2 (Timer A0 capture/compare output), ADC channel A2, and Veref- (ADC negative reference input). |
| 10 | P1.3 | bidirectional | General-purpose I/O port P1.3; multiplexed with UCB0SOMI (SPI slave out/master in), UCB0SCL (I2C clock), MCLK (main clock output), and ADC channel A3. |
| 11 | P2.2 | bidirectional | General-purpose I/O port P2.2; multiplexed with ACLK (auxiliary clock input/output). |
| 12 | P3.0 | bidirectional | General-purpose I/O port P3.0. |
| 13 | P2.3 | bidirectional | General-purpose I/O port P2.3. |
| 14 | P3.1 | bidirectional | General-purpose I/O port P3.1; multiplexed with UCA1STE (eUSCI_A1 SPI slave transmit enable). |
| 15 | P2.4 | bidirectional | General-purpose I/O port P2.4; multiplexed with UCA1CLK (eUSCI_A1 SPI/UART clock). |
| 16 | P2.5 | bidirectional | General-purpose I/O port P2.5; multiplexed with UCA1RXD (UART receive) and UCA1SOMI (SPI slave out/master in). |
| 17 | P2.6 | bidirectional | General-purpose I/O port P2.6; multiplexed with UCA1TXD (UART transmit) and UCA1SIMO (SPI slave in/master out). |
| 18 | DVSS | power_in | Ground (power supply return) connection for the device. |
| 19 | P2.7 | bidirectional | General-purpose I/O port P2.7. |
| 20 | P3.2 | bidirectional | General-purpose I/O port P3.2. |
| 21 | P2.0 | bidirectional | General-purpose I/O port P2.0; multiplexed with XOUT (output terminal for 32kHz crystal oscillator). |
| 22 | P2.1 | bidirectional | General-purpose I/O port P2.1; multiplexed with XIN (input terminal for 32kHz crystal oscillator). |
| 23 | DVSS | power_in | Ground (power supply return) connection for the device. |
| 24 | DVCC | power_in | Positive power supply input with voltage range of 1.8V to 3.6V for the device. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24-EP(4x4) |
| Category | Embedded Processors & Controllers |
| Pins | 25 |
CAD (KiCad official)
- Symbol:
MSP430FR2433IRGER - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
msp430fr2433irger-etched.step/msp430fr2433irger-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430fr2433irger.step/msp430fr2433irger.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (92 pp, sha256
92929a1a0a328b34, retrieved 2026-09-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).