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MSP430FR2311IPW20R
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Texas Instruments Microcontrollers (MCU/MPU/SOC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430FR2311IPW20R
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · TSSOP-20
MSP430FR2311IPW20R from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.1 | bidirectional | General-purpose I/O (reset default OFF after BOR) multiplexed with eUSCI_B0 clock, ACLK output, comparator input C1 and ADC input A1; all I/O can be configured as capacitive-touch I/O. |
| 2 | P1.0 | bidirectional | General-purpose I/O (reset default OFF after BOR) multiplexed with eUSCI_B0 STE, SMCLK output, comparator input C0, ADC input A0 and ADC positive reference Veref+. |
| 3 | TEST | input | Test mode pin used for selected digital I/O on the JTAG pins; it always has an internal pulldown enabled and should be left open if unused. |
| 4 | RST/NMI/SBWTDIO | bidirectional | Active-low reset input (RST, reset default pullup) that can also be configured as the nonmaskable interrupt input NMI or as the Spy-Bi-Wire data pin SBWTDIO; when unused, TI recommends DVCC through 47 kΩ pullup or internal pullup with 10 nF (or 1.1 nF with SBW) pulldown. |
| 5 | DVCC | power_in | Main supply pin for the digital and analog modules; the datasheet specifies 1.8 V to 3.6 V with a 4.7 µF to 10 µF bypass capacitor and 0.1 µF decoupling capacitor recommended. |
| 6 | DVSS | power_in | Ground reference for the device supply, connected to the power ground of DVCC. |
| 7 | P2.7/TB0CLK/XIN | bidirectional | General-purpose I/O (reset default OFF) that can also serve as Timer_B0 clock input TB0CLK or as the input terminal XIN for the crystal oscillator. |
| 8 | P2.6/MCLK/XOUT | bidirectional | General-purpose I/O (reset default OFF) that can also serve as the MCLK output or the output terminal XOUT for the crystal oscillator. |
| 9 | P2.5/UCB0SOMI/UCB0SCL | bidirectional | General-purpose I/O (reset default OFF) that can also serve as eUSCI_B0 SPI slave-out/master-in or I2C clock (SCL) when the USCIBRMP remap is selected. |
| 10 | P2.4/UCB0SIMO/UCB0SDA | bidirectional | General-purpose I/O (reset default OFF) that can also serve as eUSCI_B0 SPI slave-in/master-out or I2C data (SDA) when the USCIBRMP remap is selected. |
| 11 | P2.3/UCB0CLK/TB1TRG | bidirectional | General-purpose I/O (reset default OFF) that can also serve as eUSCI_B0 clock input/output or the Timer_B1 external trigger input TB1TRG. |
| 12 | P2.2/UCB0STE/TB1CLK | bidirectional | General-purpose I/O (reset default OFF) that can also serve as eUSCI_B0 slave transmit enable or the Timer_B1 clock input TB1CLK. |
| 13 | P2.1/TB1.2 | bidirectional | General-purpose I/O (reset default OFF) that can also serve as Timer_B1 capture/compare channel 2 (TB1.2); 20-pin package only. |
| 14 | P2.0/TB1.1/COUT | bidirectional | General-purpose I/O (reset default OFF) that can also serve as Timer_B1 capture/compare channel 1 (TB1.1) or the eCOMP0 comparator output COUT. |
| 15 | P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/TRI0+/A7/VREF+ | bidirectional | General-purpose I/O (reset default OFF) that can also serve as eUSCI_A0 UART transmit or SPI SIMO, Timer_B0 channel 2, JTAG TDO, TIA0 positive input TRI0+, ADC input A7 or the 1.5 V reference output VREF+ (pin is a PMM 1.2 V output option when A7 is used). |
| 16 | P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/TRI0-/A6 | bidirectional | General-purpose I/O (reset default OFF) that can also serve as eUSCI_A0 UART receive or SPI SOMI, Timer_B0 channel 1, JTAG TDI/TCLK, TIA0 negative input TRI0- (shared with GPIO on this package) or ADC input A6; available on the PW20 package. |
| 17 | P1.5/UCA0CLK/TMS/TRI0O/A5 | bidirectional | General-purpose I/O (reset default OFF) that can also serve as eUSCI_A0 SPI clock, JTAG TMS, TIA0 output TRI0O or ADC input A5. |
| 18 | P1.4/UCA0STE/TCK/OA0+/A4 | bidirectional | General-purpose I/O (reset default OFF) that can also serve as eUSCI_A0 SPI STE, JTAG TCK, SAC0 operational amplifier positive input OA0+ or ADC input A4. |
| 19 | P1.3/UCB0SOMI/UCB0SCL/OA0O/A3 | bidirectional | General-purpose I/O (reset default OFF) that can also serve as eUSCI_B0 SPI SOMI or I2C SCL, SAC0 operational amplifier output OA0O or ADC input A3. |
| 20 | P1.2/UCB0SIMO/UCB0SDA/TB0TRG/OA0-/A2/Veref- | bidirectional | General-purpose I/O (reset default OFF) that can also serve as eUSCI_B0 SPI SIMO or I2C SDA, Timer_B0 external trigger TB0TRG, SAC0 operational amplifier negative input OA0-, ADC input A2 or ADC negative reference Veref-. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Embedded Processors & Controllers |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
MSP430FR2311IPW20R - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
msp430fr2311ipw20r-etched.step/msp430fr2311ipw20r-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430fr2311ipw20r.step/msp430fr2311ipw20r.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (99 pp, sha256
ace23ae4fc6ae702, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).