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MSP430FR2311IPW16R
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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Datasheet
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README
markdownMSP430FR2311IPW16R
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · TSSOP-16
MSP430FR2311IPW16R from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.1/UCB0CLK/ACLK/C1/A1 | bidirectional | General-purpose digital I/O P1.1 (LVCMOS, powered from DVCC, high-impedance after BOR); alternate functions are eUSCI_B0 SPI clock I/O (UCB0CLK), ACLK output, eCOMP0 comparator input C1, and ADC analog input A1. |
| 2 | P1.0/UCB0STE/SMCLK/C0/A0/Veref+ | bidirectional | General-purpose digital I/O P1.0; alternate functions are eUSCI_B0 SPI slave transmit enable (UCB0STE), SMCLK output, eCOMP0 comparator input C0, ADC analog input A0, and ADC positive external reference input Veref+. |
| 3 | TEST/SBWTCK | input | Test-mode select input that enables the JTAG pin functions when driven high (internal pulldown always enabled; leave open if unused); also functions as the Spy-Bi-Wire clock input (SBWTCK) for 2-wire programming/debug. |
| 4 | RST/NMI/SBWTDIO | bidirectional | Active-low reset input (RST, default) that can be reconfigured as an edge-selectable non-maskable interrupt input (NMI); also serves as the bidirectional Spy-Bi-Wire data line (SBWTDIO) during 2-wire debug/programming; if unused, tie to DVCC through a 47-kΩ pullup with a 10-nF (or 1.1-nF for SBW) pulldown capacitor. |
| 5 | DVCC | power_in | Main digital/analog power-supply pin; recommended supply range is 1.8 V to 3.6 V with a 4.7 µF to 10 µF bulk capacitor plus a 100 nF low-ESR ceramic decoupling capacitor placed close to the pin. |
| 6 | DVSS | power_in | Digital and analog ground-supply pin (0 V reference for all other pin voltages). |
| 7 | P2.7/TB0CLK/XIN | bidirectional | General-purpose digital I/O P2.7 with pin-interrupt and LPM3.5/LPM4/LPM4.5 wake-up capability; alternate functions are Timer0_B3 external clock input (TB0CLK) and the crystal oscillator input terminal (XIN) for the LFXT/HFXT oscillator. |
| 8 | P2.6/MCLK/XOUT | bidirectional | General-purpose digital I/O P2.6; alternate functions are MCLK output and the crystal oscillator output terminal (XOUT) for the LFXT/HFXT oscillator. |
| 9 | P2.0/TB1.1/COUT | bidirectional | General-purpose digital I/O P2.0 with pin-interrupt and LPM3.5/LPM4/LPM4.5 wake-up capability; alternate functions are Timer1_B3 CCR1 capture/compare I/O (TB1.1) and the eCOMP0 comparator output (COUT). |
| 10 | P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/TRI0+/A7/VREF+ | bidirectional | General-purpose digital I/O P1.7 (shared with JTAG; TI recommends disabling the pin interrupt during JTAG debug); alternate functions are eUSCI_A0 UART transmit (UCA0TXD) or SPI master-out data (UCA0SIMO), Timer0_B3 CCR2 capture/compare I/O (TB0.2), JTAG data output (TDO), TIA0 positive input (TRI0+), ADC analog input A7, and buffered 1.2-V reference voltage output (VREF+). |
| 11 | P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/A6 | bidirectional | General-purpose digital I/O P1.6 (shared with JTAG; TI recommends disabling the pin interrupt during JTAG debug); alternate functions are eUSCI_A0 UART receive (UCA0RXD) or SPI slave-out data (UCA0SOMI), Timer0_B3 CCR1 capture/compare I/O (TB0.1), JTAG data input (TDI) or test clock (TCLK), and ADC analog input A6; note the TRI0- (TIA0 negative input) function present on this pin for the PW20/RGY packages is not available on the TSSOP-16 package, which instead provides a dedicated low-leakage TRI0- pin (pin 12). |
| 12 | TRI0- | input | Dedicated transimpedance amplifier (TIA0) negative input, unique to the TSSOP-16 package to provide low-leakage (5 pA typical) performance separate from any GPIO function; this is a high-impedance input and should be left open if unused. |
| 13 | P1.5/UCA0CLK/TMS/TRI0O/A5 | bidirectional | General-purpose digital I/O P1.5 (shared with JTAG; TI recommends disabling the pin interrupt during JTAG debug); alternate functions are eUSCI_A0 SPI clock I/O (UCA0CLK), JTAG test-mode select (TMS), TIA0 output (TRI0O), and ADC analog input A5. |
| 14 | P1.4/UCA0STE/TCK/OA0+/A4 | bidirectional | General-purpose digital I/O P1.4 (shared with JTAG; TI recommends disabling the pin interrupt during JTAG debug); alternate functions are eUSCI_A0 SPI slave transmit enable (UCA0STE), JTAG test clock input (TCK), SAC0 operational-amplifier positive input (OA0+), and ADC analog input A4. |
| 15 | P1.3/UCB0SOMI/UCB0SCL/OA0O/A3 | bidirectional | General-purpose digital I/O P1.3; alternate functions are eUSCI_B0 SPI slave-out data (UCB0SOMI) or I2C clock (UCB0SCL), SAC0 operational-amplifier output (OA0O), and ADC analog input A3. |
| 16 | P1.2/UCB0SIMO/UCB0SDA/TB0TRG/OA0-/A2/Veref- | bidirectional | General-purpose digital I/O P1.2; alternate functions are eUSCI_B0 SPI master-out data (UCB0SIMO) or I2C data (UCB0SDA), Timer0_B3 external high-impedance trigger input (TB0TRG), SAC0 operational-amplifier negative input (OA0-), ADC analog input A2, and ADC negative external reference input Veref-. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Embedded Processors & Controllers |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
MSP430FR2311IPW16R - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
msp430fr2311ipw16r-etched.step/msp430fr2311ipw16r-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430fr2311ipw16r.step/msp430fr2311ipw16r.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (99 pp, sha256
ace23ae4fc6ae702, retrieved 2026-09-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).