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MSP430FR2153TRSMR
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Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-32-EP(4x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430FR2153TRSMR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-32-EP(4x4)
MSP430FR2153TRSMR from Texas Instruments, in a VQFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.1/UCB0CLK/ACLK/COMP0.1/A1 | bidirectional | General-purpose digital I/O P1.1, alternatively the eUSCI_B0 SPI clock (UCB0CLK), ACLK output, eCOMP0 comparator input COMP0.1, or 12-bit ADC analog input channel A1. |
| 2 | P1.0/UCB0STE/SMCLK/COMP0.0/A0/Veref+ | bidirectional | General-purpose digital I/O P1.0, alternatively the eUSCI_B0 SPI slave-transmit-enable (UCB0STE), SMCLK output, eCOMP0 input COMP0.0, ADC channel A0, or the ADC positive external reference output Veref+. |
| 3 | TEST/SBWTCK | input | Dedicated test-mode select input (has an internal pulldown that is always enabled) that also functions as the Spy-Bi-Wire test clock (SBWTCK) used for two-wire JTAG programming and debug. |
| 4 | RST/NMI/SBWTDIO | bidirectional | Active-low device reset input or non-maskable-interrupt input (RST/NMI) that also serves as the bidirectional Spy-Bi-Wire test data I/O line (SBWTDIO); the recommended termination when unused is a 47-kΩ pull-up (or internal pull-up) with a 10-nF (or 1.1-nF) pulldown. |
| 5 | DVCC | power_in | Digital supply voltage input to the device, recommended operating range 1.8 V to 3.6 V, with a 4.7 µF to 10 µF low-ESR decoupling capacitor recommended close to the pin. |
| 6 | DVSS | power_in | Digital ground (0 V) reference return for the DVCC supply. |
| 7 | P2.7/TB0CLK/XIN | bidirectional | General-purpose digital I/O P2.7, alternatively the external timer clock input for Timer0_B3 (TB0CLK) or the low-frequency crystal oscillator input (XIN) for LFXT. |
| 8 | P2.6/MCLK/XOUT | bidirectional | General-purpose digital I/O P2.6, alternatively the MCLK output or the low-frequency crystal oscillator output (XOUT) for LFXT. |
| 9 | P2.5/COMP1.0 | bidirectional | General-purpose digital I/O P2.5, alternatively an analog input to enhanced comparator eCOMP1 (COMP1.0). |
| 10 | P2.4/COMP1.1 | bidirectional | General-purpose digital I/O P2.4, alternatively an analog input to enhanced comparator eCOMP1 (COMP1.1). |
| 11 | P4.7/UCB1SCL | bidirectional | General-purpose digital I/O P4.7, alternatively the eUSCI_B1 I2C clock line (UCB1SCL); on this 32-pin package eUSCI_B1 supports the I2C function only. |
| 12 | P4.6/UCB1SDA | bidirectional | General-purpose digital I/O P4.6, alternatively the eUSCI_B1 I2C data line (UCB1SDA). |
| 13 | P4.3/UCA1TXD/UCA1SIMO/UCA1TXD | bidirectional | General-purpose digital I/O P4.3, alternatively the eUSCI_A1 UART transmit data line (UCA1TXD, normal or inverted polarity) or SPI slave-in/master-out (UCA1SIMO). |
| 14 | P4.2/UCA1RXD/UCA1SOMI/UCA1RXD | bidirectional | General-purpose digital I/O P4.2, alternatively the eUSCI_A1 UART receive data line (UCA1RXD, normal or inverted polarity) or SPI slave-out/master-in (UCA1SOMI). |
| 15 | P4.1/UCA1CLK | bidirectional | General-purpose digital I/O P4.1, alternatively the eUSCI_A1 SPI clock (UCA1CLK). |
| 16 | P4.0/UCA1STE/ISOTXD/ISORXD | bidirectional | General-purpose digital I/O P4.0, alternatively the eUSCI_A1 SPI slave-transmit-enable (UCA1STE) or the IrDA transmit/receive lines (ISOTXD/ISORXD). |
| 17 | P2.1/TB1.2/COMP1.O | bidirectional | General-purpose digital I/O P2.1, alternatively Timer1_B3 capture/compare register 2 (TB1.2: capture input CCI2A or compare output Out2) or the eCOMP1 comparator output (COMP1.O). |
| 18 | P2.0/TB1.1/COMP0.O | bidirectional | General-purpose digital I/O P2.0, alternatively Timer1_B3 capture/compare register 1 (TB1.1: capture input CCI1A or compare output Out1) or the eCOMP0 comparator output (COMP0.O). |
| 19 | P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/A7/VREF+ | bidirectional | General-purpose digital I/O P1.7, alternatively eUSCI_A0 UART TXD or SPI SIMO, Timer0_B3 CCR2 (TB0.2), JTAG TDO output, ADC channel A7, or (when selected) the PMM 1.2-V reference output VREF+ measurable on A7. |
| 20 | P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/A6 | bidirectional | General-purpose digital I/O P1.6, alternatively eUSCI_A0 UART RXD or SPI SOMI, Timer0_B3 CCR1 (TB0.1), JTAG TDI/TCLK input, or ADC channel A6. |
| 21 | P1.5/UCA0CLK/TMS/A5 | bidirectional | General-purpose digital I/O P1.5, alternatively the eUSCI_A0 SPI clock (UCA0CLK), the JTAG TMS input, or ADC channel A5. |
| 22 | P1.4/UCA0STE/TCK/A4 | bidirectional | General-purpose digital I/O P1.4, alternatively the eUSCI_A0 SPI slave-transmit-enable (UCA0STE), the JTAG TCK input, or ADC channel A4. |
| 23 | P3.7 | bidirectional | General-purpose digital I/O P3.7; on the MSP430FR215x (no SAC) this pin has no alternate analog/peripheral function shown in the pinout. |
| 24 | P3.6 | bidirectional | General-purpose digital I/O P3.6; on the MSP430FR215x (no SAC) this pin has no alternate analog/peripheral function shown in the pinout. |
| 25 | P3.5 | bidirectional | General-purpose digital I/O P3.5; on the MSP430FR215x (no SAC) this pin has no alternate analog/peripheral function shown in the pinout. |
| 26 | P3.4/SMCLK | bidirectional | General-purpose digital I/O P3.4, alternatively the SMCLK output. |
| 27 | P3.3 | bidirectional | General-purpose digital I/O P3.3; on the MSP430FR215x (no SAC) this pin has no alternate analog/peripheral function shown in the pinout. |
| 28 | P3.2 | bidirectional | General-purpose digital I/O P3.2; on the MSP430FR215x (no SAC) this pin has no alternate analog/peripheral function shown in the pinout. |
| 29 | P3.1 | bidirectional | General-purpose digital I/O P3.1; on the MSP430FR215x (no SAC) this pin has no alternate analog/peripheral function shown in the pinout. |
| 30 | P3.0/MCLK | bidirectional | General-purpose digital I/O P3.0, alternatively the MCLK output. |
| 31 | P1.3/UCB0SOMI/UCB0SCL/A3 | bidirectional | General-purpose digital I/O P1.3, alternatively the eUSCI_B0 SPI SOMI or I2C SCL line (UCB0SOMI/UCB0SCL), or ADC channel A3. |
| 32 | P1.2/UCB0SIMO/UCB0SDA/TB0TRG/A2/Veref- | bidirectional | General-purpose digital I/O P1.2, alternatively the eUSCI_B0 SPI SIMO or I2C SDA line (UCB0SIMO/UCB0SDA), the Timer0_B3 external trigger input (TB0TRG) for TB0OUTH, ADC channel A2, or the ADC negative external reference input Veref-. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32-EP(4x4) |
| Category | Embedded Processors & Controllers |
| Pins | 33 |
CAD (KiCad official)
- Symbol:
MSP430FR2153TRSMR - Footprint:
Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm - 3D model: VQFN-32-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
msp430fr2153trsmr-etched.step/msp430fr2153trsmr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430fr2153trsmr.step/msp430fr2153trsmr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (146 pp, sha256
20e2c81ab11138f8, retrieved 2026-09-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).