# MSP430FR2100IRLLR

**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · HVQFN-24-EP(3x3)

MSP430FR2100IRLLR from Texas Instruments, in a HVQFN-24-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TEST | input | Test-mode pin that enables the JTAG and Spy-Bi-Wire interface (SBWTCK), always has an enabled internal pull-down, and is left unconnected when unused. |
| 2 | RST/NMI/SBWTDIO | bidirectional | Active-low reset input by default (configurable as NMI, and carrying Spy-Bi-Wire data); when unused it needs a 47 kΩ pull-up to DVCC or the internal pull-up, with a pull-down capacitor no larger than 10 nF (1.1 nF when using TI tools). |
| 3 | DVCC | power_in | Main supply for the digital and analog modules, specified at 1.8 V to 3.6 V, with 10 µF and 100 nF low-ESR decoupling placed within a few millimeters of the pin. |
| 4 | DVSS | power_in | Ground reference for the device; VSS is specified as 0 V. |
| 5 | P2.7/TB0CLK/XIN | bidirectional | General-purpose I/O with Timer_B TB0CLK clock input and XIN input for the external 32 kHz crystal (LFXT, 32768 Hz only). |
| 6 | NC | unconnected | Not connected internally (NC). |
| 7 | P2.6/MCLK/XOUT | bidirectional | General-purpose I/O with MCLK output and XOUT output for the external 32 kHz crystal; port clock output is specified up to 16 MHz. |
| 8 | P2.0/TB0.1/COUT | bidirectional | General-purpose I/O with Timer_B TB0.1 capture/compare input or output and eCOMP0 comparator output COUT. |
| 9 | NC | unconnected | Not connected internally (NC). |
| 10 | NC | unconnected | Not connected internally (NC). |
| 11 | P2.1/TB0.2 | bidirectional | General-purpose I/O with Timer_B TB0.2 capture/compare input or output. |
| 12 | NC | unconnected | Not connected internally (NC). |
| 13 | P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/A7/VREF+ | bidirectional | General-purpose I/O multiplexed with eUSCI_A0 UART TXD or SPI SIMO, Timer_B TB0.2, JTAG TDO, ADC input A7 and the 1.2 V reference output VREF+ when enabled. |
| 14 | P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/A6 | bidirectional | General-purpose I/O multiplexed with eUSCI_A0 UART RXD or SPI SOMI, Timer_B TB0.1, JTAG TDI/TCLK, and ADC input A6. |
| 15 | P1.5/UCA0CLK/TMS/A5 | bidirectional | General-purpose I/O multiplexed with eUSCI_A0 SPI clock, JTAG TMS, and ADC input A5. |
| 16 | P1.4/UCA0STE/TCK/A4 | bidirectional | General-purpose I/O multiplexed with eUSCI_A0 SPI STE, JTAG TCK, and ADC input A4. |
| 17 | P1.3/UCA0TXD/UCA0SIMO/C3/A3 | bidirectional | General-purpose I/O multiplexed with eUSCI_A0 UART TXD or SPI SIMO, eCOMP0 comparator input C3, and ADC input A3. |
| 18 | NC | unconnected | Not connected internally (NC). |
| 19 | P1.2/UCA0RXD/UCA0SOMI/TB0TRG/C2/A2/Veref- | bidirectional | General-purpose I/O multiplexed with eUSCI_A0 UART RXD or SPI SOMI, Timer_B external trigger TB0TRG, eCOMP0 input C2, ADC input A2, and ADC negative reference Veref-. |
| 20 | P1.0/UCA0STE/SMCLK/C0/A0/Veref+ | bidirectional | General-purpose I/O multiplexed with eUSCI_A0 SPI STE, SMCLK output, eCOMP0 input C0, ADC input A0, and ADC positive reference Veref+. |
| 21 | NC | unconnected | Not connected internally (NC). |
| 22 | NC | unconnected | Not connected internally (NC). |
| 23 | P1.1/UCA0CLK/ACLK/C1/A1 | bidirectional | General-purpose I/O multiplexed with eUSCI_A0 SPI clock, ACLK output, eCOMP0 input C1, and ADC input A1. |
| 24 | NC | unconnected | Not connected internally (NC). |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HVQFN-24-EP(3x3) |
| Category | Embedded Processors & Controllers |
| Pins | 25 |

## CAD (KiCad official)

- Symbol: `MSP430FR2100IRLLR`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_3x3mm_P0.4mm_EP1.75x1.6mm`
- 3D model: HVQFN-24-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `msp430fr2100irllr-etched.step` / `msp430fr2100irllr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430fr2100irllr.step` / `msp430fr2100irllr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430fr2100) (87 pp, sha256 `7505f67fee2c23fa`, retrieved 2026-10-11, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/msp430fr2100irllr-datasheet.pdf)