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Contents

README

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MSP430FR2033IPMR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

MSP430FR2033IPMR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P4.7 bidirectional General-purpose I/O P4.7 with capacitive-touch capability; if unused, leave open and set to output direction (PxDIR.n = 1).
2 P4.6 bidirectional General-purpose I/O P4.6 with capacitive-touch capability; if unused, leave open and set to output direction (PxDIR.n = 1).
3 P4.5 bidirectional General-purpose I/O P4.5 with capacitive-touch capability; if unused, leave open and set to output direction (PxDIR.n = 1).
4 P4.4 bidirectional General-purpose I/O P4.4 with capacitive-touch capability; if unused, leave open and set to output direction (PxDIR.n = 1).
5 P4.3 bidirectional General-purpose I/O P4.3 with capacitive-touch capability; if unused, leave open and set to output direction (PxDIR.n = 1).
6 P4.2/XOUT bidirectional General-purpose I/O P4.2, or output terminal of the 32-kHz crystal oscillator (XT1); only a low-frequency 32 kHz crystal is supported.
7 P4.1/XIN bidirectional General-purpose I/O P4.1, or input terminal of the 32-kHz crystal oscillator (XT1); a digital clock may be applied here in XT1BYPASS mode.
8 DVSS power_in Ground supply pin for the digital and analog modules (0 V).
9 DVCC power_in Main supply pin for the digital and analog modules; 1.8 V to 3.6 V, with a recommended 4.7 µF to 10 µF capacitor at DVCC.
10 RST/NMI/SBWTDIO bidirectional Active-low reset input, nonmaskable interrupt input, or Spy-Bi-Wire data input/output; unused pin should be pulled up to DVCC (47 kΩ or internal pullup) with a 10 nF (or 1.1 nF) pulldown.
11 TEST/SBWTCK input Test mode pin, which also serves as the Spy-Bi-Wire input clock; it always has an internal pulldown enabled and may be left open when unused.
12 P4.0/TA1.1 bidirectional General-purpose I/O P4.0, or Timer TA1 CCR1 capture input (CCI1A) / compare output (Out1).
13 P8.3/TA1.2 bidirectional General-purpose I/O P8.3, or Timer TA1 CCR2 capture input (CCI2A) / compare output (Out2); available only in the LQFP-64 package.
14 P8.2/TA1CLK bidirectional General-purpose I/O P8.2, or external timer clock input TACLK for Timer TA1; available only in the LQFP-64 package.
15 P8.1/ACLK/A9 bidirectional General-purpose I/O P8.1, ACLK output, or ADC analog input A9; available only in the LQFP-64 package.
16 P8.0/SMCLK/A8 bidirectional General-purpose I/O P8.0, SMCLK output, or ADC analog input A8; available only in the LQFP-64 package.
17 P1.7/TA0.1/TDO/A7 bidirectional General-purpose I/O P1.7 (interrupt-capable), or Timer TA0 CCR1 capture/compare output, JTAG test data output TDO, or ADC analog input A7; disable the pin interrupt during JTAG debug.
18 P1.6/TA0.2/TDI/TCLK/A6 bidirectional General-purpose I/O P1.6 (interrupt-capable), or Timer TA0 CCR2 capture/compare output, JTAG test data input or test clock TDI/TCLK, or ADC analog input A6; disable the pin interrupt during JTAG debug.
19 P1.5/TA0CLK/TMS/A5 bidirectional General-purpose I/O P1.5 (interrupt-capable), or Timer TA0 external clock input TA0CLK, JTAG test mode select TMS, or ADC analog input A5.
20 P1.4/MCLK/TCK/A4/VREF+ bidirectional General-purpose I/O P1.4 (interrupt-capable), or MCLK output, JTAG test clock TCK, or ADC analog input A4 / positive reference VREF+.
21 P1.3/UCA0STE/A3 bidirectional General-purpose I/O P1.3 (interrupt-capable), or eUSCI_A0 STE (SPI slave transmit enable), or ADC analog input A3.
22 P1.2/UCA0CLK/A2 bidirectional General-purpose I/O P1.2 (interrupt-capable), or eUSCI_A0 clock (UART/SPI SCLK), or ADC analog input A2.
23 P1.1/UCA0RXD/UCA0SOMI/A1/Veref+ bidirectional General-purpose I/O P1.1 (interrupt-capable), or eUSCI_A0 UART RXD / SPI SOMI, or ADC analog input A1 and external positive reference Veref+.
24 P1.0/UCA0TXD/UCA0SIMO/A0/Veref- bidirectional General-purpose I/O P1.0 (interrupt-capable), or eUSCI_A0 UART TXD / SPI SIMO, or ADC analog input A0 and external negative reference Veref-.
25 P5.7 bidirectional General-purpose I/O P5.7 with capacitive-touch capability; if unused, leave open and set to output direction.
26 P5.6 bidirectional General-purpose I/O P5.6 with capacitive-touch capability; if unused, leave open and set to output direction.
27 P5.5 bidirectional General-purpose I/O P5.5 with capacitive-touch capability; if unused, leave open and set to output direction.
28 P5.4 bidirectional General-purpose I/O P5.4 with capacitive-touch capability; if unused, leave open and set to output direction.
29 P5.3/UCB0SOMI/UCB0SCL bidirectional General-purpose I/O P5.3, or eUSCI_B0 SPI SOMI or I2C clock SCL.
30 P5.2/UCB0SIMO/UCB0SDA bidirectional General-purpose I/O P5.2, or eUSCI_B0 SPI SIMO or I2C data SDA.
31 P5.1/UCB0CLK bidirectional General-purpose I/O P5.1, or eUSCI_B0 SPI clock (SCLK).
32 P5.0/UCB0STE bidirectional General-purpose I/O P5.0, or eUSCI_B0 SPI STE.
33 P2.7 bidirectional General-purpose I/O P2.7 (interrupt-capable, can wake the MCU from LPM3.5) with capacitive-touch capability.
34 P2.6 bidirectional General-purpose I/O P2.6 (interrupt-capable, can wake the MCU from LPM3.5) with capacitive-touch capability.
35 P2.5 bidirectional General-purpose I/O P2.5 (interrupt-capable, can wake the MCU from LPM3.5) with capacitive-touch capability.
36 P2.4 bidirectional General-purpose I/O P2.4 (interrupt-capable, can wake the MCU from LPM3.5) with capacitive-touch capability.
37 P2.3 bidirectional General-purpose I/O P2.3 (interrupt-capable, can wake the MCU from LPM3.5) with capacitive-touch capability.
38 P2.2 bidirectional General-purpose I/O P2.2 (interrupt-capable, can wake the MCU from LPM3.5) with capacitive-touch capability.
39 P2.1 bidirectional General-purpose I/O P2.1 (interrupt-capable, can wake the MCU from LPM3.5) with capacitive-touch capability.
40 P2.0 bidirectional General-purpose I/O P2.0 (interrupt-capable, can wake the MCU from LPM3.5) with capacitive-touch capability.
41 P6.7 bidirectional General-purpose I/O P6.7 with capacitive-touch capability; available only in the LQFP-64 package.
42 P6.6 bidirectional General-purpose I/O P6.6 with capacitive-touch capability; available only in the LQFP-64 package.
43 P6.5 bidirectional General-purpose I/O P6.5 with capacitive-touch capability.
44 P6.4 bidirectional General-purpose I/O P6.4 with capacitive-touch capability.
45 P6.3 bidirectional General-purpose I/O P6.3 with capacitive-touch capability.
46 P6.2 bidirectional General-purpose I/O P6.2 with capacitive-touch capability.
47 P6.1 bidirectional General-purpose I/O P6.1 with capacitive-touch capability.
48 P6.0 bidirectional General-purpose I/O P6.0 with capacitive-touch capability.
49 P3.7 bidirectional General-purpose I/O P3.7 with capacitive-touch capability.
50 P3.6 bidirectional General-purpose I/O P3.6 with capacitive-touch capability.
51 P3.5 bidirectional General-purpose I/O P3.5 with capacitive-touch capability.
52 P3.4 bidirectional General-purpose I/O P3.4 with capacitive-touch capability.
53 P3.3 bidirectional General-purpose I/O P3.3 with capacitive-touch capability.
54 P3.2 bidirectional General-purpose I/O P3.2 with capacitive-touch capability.
55 P3.1 bidirectional General-purpose I/O P3.1 with capacitive-touch capability.
56 P3.0 bidirectional General-purpose I/O P3.0 with capacitive-touch capability.
57 P7.7 bidirectional General-purpose I/O P7.7 with capacitive-touch capability; available only in the LQFP-64 package.
58 P7.6 bidirectional General-purpose I/O P7.6 with capacitive-touch capability; available only in the LQFP-64 package.
59 P7.5 bidirectional General-purpose I/O P7.5 with capacitive-touch capability; available only in the LQFP-64 package.
60 P7.4 bidirectional General-purpose I/O P7.4 with capacitive-touch capability; available only in the LQFP-64 package.
61 P7.3 bidirectional General-purpose I/O P7.3 with capacitive-touch capability.
62 P7.2 bidirectional General-purpose I/O P7.2 with capacitive-touch capability.
63 P7.1 bidirectional General-purpose I/O P7.1 with capacitive-touch capability.
64 P7.0 bidirectional General-purpose I/O P7.0 with capacitive-touch capability.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: MSP430FR2033IPMR
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: msp430fr2033ipmr-etched.step / msp430fr2033ipmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430fr2033ipmr.step / msp430fr2033ipmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (99 pp, sha256 6220799f5c3a8c78, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF