# MSP430FG478IPNR

**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)

MSP430FG478IPNR from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DVCC1 | power_in | Digital supply voltage, positive terminal; supplies all digital parts. |
| 2 | P2.2/TB1 | bidirectional | General-purpose digital I/O pin; Timer_B3 capture CCI1A/B input and compare Out1 output. |
| 3 | P2.1/TB0/S0 | bidirectional | General-purpose digital I/O pin; Timer_B capture CCI0A/B input and compare Out0 output; LCD segment output S0. |
| 4 | P2.0/TA2/S1 | bidirectional | General-purpose digital I/O pin; Timer_A capture CCI2A/B input and compare Out2 output; LCD segment output S1. |
| 5 | P2.6/CAOUT/S2 | bidirectional | General-purpose digital I/O pin; Comparator_A output; LCD segment output S2. |
| 6 | P2.7/S3 | bidirectional | General-purpose digital I/O pin; LCD segment output S3. |
| 7 | GND | power_in | Ground pin used to shield the oscillator; it is recommended to connect GND externally to DVSS. |
| 8 | XIN | input | Input port for crystal oscillator XT1; standard or watch crystals can be connected. |
| 9 | XOUT | output | Output port for crystal oscillator XT1; standard or watch crystals can be connected. |
| 10 | GND | power_in | Ground pin used to shield the oscillator; it is recommended to connect GND externally to DVSS. |
| 11 | P4.7/S4 | bidirectional | General-purpose digital I/O pin; LCD segment output S4. |
| 12 | P4.6/S5 | bidirectional | General-purpose digital I/O pin; LCD segment output S5. |
| 13 | P4.5/S6 | bidirectional | General-purpose digital I/O pin; LCD segment output S6. |
| 14 | P4.4/S7 | bidirectional | General-purpose digital I/O pin; LCD segment output S7. |
| 15 | P4.3/S8 | bidirectional | General-purpose digital I/O pin; LCD segment output S8. |
| 16 | P4.2/S9 | bidirectional | General-purpose digital I/O pin; LCD segment output S9. |
| 17 | P4.1/S10 | bidirectional | General-purpose digital I/O pin; LCD segment output S10. |
| 18 | P4.0/S11 | bidirectional | General-purpose digital I/O pin; LCD segment output S11. |
| 19 | S12 | output | LCD segment output 12. |
| 20 | S13 | output | LCD segment output 13. |
| 21 | S14 | output | LCD segment output 14. |
| 22 | S15 | output | LCD segment output 15. |
| 23 | S16 | output | LCD segment output 16. |
| 24 | S17 | output | LCD segment output 17. |
| 25 | S18 | output | LCD segment output 18. |
| 26 | S19 | output | LCD segment output 19. |
| 27 | P5.0/S20 | bidirectional | General-purpose digital I/O pin; LCD segment output S20. |
| 28 | P5.1/S21 | bidirectional | General-purpose digital I/O pin; LCD segment output S21. |
| 29 | S22 | output | LCD segment output 22. |
| 30 | S23 | output | LCD segment output 23. |
| 31 | S24 | output | LCD segment output 24. |
| 32 | S25 | output | LCD segment output 25. |
| 33 | COM0 | output | Common output; COM0 to COM3 are used for LCD backplanes. |
| 34 | P5.2/COM1 | bidirectional | General-purpose digital I/O pin; LCD common output COM1. |
| 35 | P5.3/COM2 | bidirectional | General-purpose digital I/O pin; LCD common output COM2. |
| 36 | P5.4/COM3 | bidirectional | General-purpose digital I/O pin; LCD common output COM3. |
| 37 | LCDCAP/R33 | bidirectional | Capacitor connection for the LCD charge pump; input port for the most positive analog LCD level (V4). |
| 38 | P5.5/R23 | bidirectional | General-purpose digital I/O pin; input port for the second most positive analog LCD level (V3). |
| 39 | P5.6/LCDREF/R13 | bidirectional | General-purpose digital I/O pin; external LCD reference voltage input; input port for the third most positive analog LCD level (V3 or V2). |
| 40 | P5.7/R03 | bidirectional | General-purpose digital I/O pin; input port for the fourth most positive analog LCD level (V1). |
| 41 | P3.0/UCB0STE/UCA0CLK | bidirectional | General-purpose digital I/O pin; USCI B0 slave transmit enable; USCI A0 clock input/output. |
| 42 | P3.1/UCB0SIMO/UCB0SDA/S26 | bidirectional | General-purpose digital I/O pin; USCI B0 slave in/master out in SPI mode or SDA I2C data; LCD segment output S26. |
| 43 | P3.2/UCB0SOMI/UCB0SCL/S27 | bidirectional | General-purpose digital I/O pin; USCI B0 slave out/master in in SPI mode or SCL I2C clock; LCD segment output S27. |
| 44 | P3.3/UCB0CLK/UCA0STE | bidirectional | General-purpose digital I/O pin; USCI B0 clock input/output; USCI A0 slave transmit enable. |
| 45 | P3.4/S28 | bidirectional | General-purpose digital I/O pin; LCD segment output S28. |
| 46 | P3.5/S29 | bidirectional | General-purpose digital I/O pin; LCD segment output S29. |
| 47 | P3.6/S30 | bidirectional | General-purpose digital I/O pin; LCD segment output S30. |
| 48 | P3.7/S31 | bidirectional | General-purpose digital I/O pin; LCD segment output S31. |
| 49 | P1.7/CA1/A2+ | bidirectional | General-purpose digital I/O pin; Comparator_A input 1; SD16 positive analog input A2. |
| 50 | P1.6/CA0/A2-/OA0I0/DAC0 | bidirectional | General-purpose digital I/O pin; Comparator_A input 0; SD16 negative analog input A2; OA0 analog input I0; DAC12.0 output. |
| 51 | P1.5/TACLK/ACLK/A3+ | bidirectional | General-purpose digital I/O pin; Timer_A clock TACLK input; ACLK signal output; SD16 positive analog input A3. |
| 52 | AVCC | power_in | Analog supply voltage, positive terminal. |
| 53 | AVSS | power_in | Analog supply voltage, negative terminal. |
| 54 | P1.4/TBCLK/SMCLK/A3-/OA1I0/DAC1 | bidirectional | General-purpose digital I/O pin; Timer_B clock TBCLK input; SMCLK signal output; SD16 negative analog input A3; OA1 analog input I0; DAC12.1 output. |
| 55 | P1.3/TBOUTH/SVSOUT/A4+/OA1I3 | bidirectional | General-purpose digital I/O pin; Timer_B TBOUTH high-impedance control of TB0 to TB2 outputs; SVS comparator output; SD16 positive analog input A4; OA1 analog input I3. |
| 56 | P1.2/TA1/A4-/OA0I3 | bidirectional | General-purpose digital I/O pin; Timer_A capture CCI1A input and compare Out1 output; SD16 negative analog input A4; OA0 analog input I3. |
| 57 | P1.1/TA0/MCLK/OA1RFB | bidirectional | General-purpose digital I/O pin; Timer_A capture CCI0B input and compare Out0 output; MCLK signal output; range switch to OA1 output; BSL receive. |
| 58 | P1.0/TA0/OA0RFB | bidirectional | General-purpose digital I/O pin; Timer_A capture CCI0A input and compare Out0 output; range switch to OA0 output; BSL transmit. |
| 59 | P6.7/OA1I2/SVSIN | bidirectional | General-purpose digital I/O pin; OA1 analog input I2; SVS input. |
| 60 | VREF | power_in | Input for an external reference voltage or internal reference voltage output. |
| 61 | P6.6/OA1I1 | bidirectional | General-purpose digital I/O pin; OA1 analog input I1. |
| 62 | P6.5/OA0I2 | bidirectional | General-purpose digital I/O pin; OA0 analog input I2. |
| 63 | P6.4/A1-/OA1FB | bidirectional | General-purpose digital I/O pin; SD16 negative analog input A1; OA1 analog input feedback. |
| 64 | P6.3/A1+/OA1O | bidirectional | General-purpose digital I/O pin; SD16 positive analog input A1; OA1 output. |
| 65 | P6.2/OA0I1 | bidirectional | General-purpose digital I/O pin; OA0 analog input I1. |
| 66 | P6.1/A0-/OA0FB | bidirectional | General-purpose digital I/O pin; SD16 negative analog input A0; OA0 analog input feedback. |
| 67 | P6.0/A0+/OA0O | bidirectional | General-purpose digital I/O pin; SD16 positive analog input A0; OA0 output. |
| 68 | XT2OUT | output | Output terminal of crystal oscillator XT2. |
| 69 | XT2IN | input | Input port for crystal oscillator XT2. |
| 70 | TDO/TDI | bidirectional | Test data output port; TDO/TDI data output or programming data input terminal. |
| 71 | TDI/TCLK | input | Test data input or test clock input; the device protection fuse is connected to TDI/TCLK. |
| 72 | TMS | input | Test mode select; used as an input port for device programming and test. |
| 73 | TCK | input | Test clock (JTAG); clock input port for device programming, test and bootloader start. |
| 74 | RST/NMI | input | Reset input, nonmaskable interrupt input port, or bootloader start (in flash devices). |
| 75 | P2.5/UCA0RXD/UCA0SOMI | bidirectional | General-purpose digital I/O pin; USCI A0 receive data input in UART mode or slave data out/master in in SPI mode. |
| 76 | P2.4/UCA0TXD/UCA0SIMO | bidirectional | General-purpose digital I/O pin; USCI A0 transmit data output in UART mode or slave data in/master out in SPI mode. |
| 77 | P2.3/TB2 | bidirectional | General-purpose digital I/O pin; Timer_B capture CCI2A/B input and compare Out2 output. |
| 78 | DVSS2 | power_in | Digital supply voltage, negative terminal; supplies all digital parts. |
| 79 | DVSS1 | power_in | Digital supply voltage, negative terminal; supplies all digital parts. |
| 80 | DVCC2 | power_in | Digital supply voltage, positive terminal; supplies all digital parts. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-80(12x12) |
| Category | Embedded Processors & Controllers |
| Pins | 80 |

## CAD (KiCad official)

- Symbol: `MSP430FG478IPNR`
- Footprint: `Package_QFP:LQFP-80_12x12mm_P0.5mm`
- 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
- 3D model files: `msp430fg478ipnr-etched.step` / `msp430fg478ipnr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430fg478ipnr.step` / `msp430fg478ipnr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430fg479) (103 pp, sha256 `2029b4644174a9cd`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/msp430fg478ipnr-datasheet.pdf)