component

MSP430FG4618IPZR

Public Made by Adom

by adom

Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersmsp430fg4618ipzrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2d ago
viewers msp430fg4618ipzr: viewers · Ray 2d ago
msp430fg4618ipzr-etched.glb msp430fg4618ipzr: factory component page (tier=lcsc) · Ray 2d ago
msp430fg4618ipzr-etched.step msp430fg4618ipzr: factory component page (tier=lcsc) · Ray 2d ago
msp430fg4618ipzr-hero.glb msp430fg4618ipzr: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
msp430fg4618ipzr-hero.overlay.json Publish 0.1.0 · Ray 2d ago
msp430fg4618ipzr.glb Publish 0.1.0 · Ray 2d ago
msp430fg4618ipzr.kicad_mod Publish 0.1.0 · Ray 2d ago
msp430fg4618ipzr.kicad_sym Publish 0.1.0 · Ray 2d ago
msp430fg4618ipzr.lbr Publish 0.1.0 · Ray 2d ago
msp430fg4618ipzr.step Publish 0.1.0 · Ray 2d ago
package.json Publish 0.1.0 · Ray 2d ago
page.json Set visibility: public · Ray 2d ago
README.md Initial commit: component/msp430fg4618ipzr · Ray 2d ago

MSP430FG4618IPZR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

MSP430FG4618IPZR from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DVCC1 power_in Digital supply voltage, positive terminal.
2 P6.3/A3/OA1O bidirectional General-purpose digital I/O, with analog input A3 to the 12-bit ADC and the OA1 output.
3 P6.4/A4/OA1I0 bidirectional General-purpose digital I/O, with analog input A4 to the 12-bit ADC and the OA1 input multiplexer on the + and − terminals.
4 P6.5/A5/OA2O bidirectional General-purpose digital I/O, with analog input A5 to the 12-bit ADC and the OA2 output.
5 P6.6/A6/DAC0/OA2I0 bidirectional General-purpose digital I/O, with analog input A6 to the 12-bit ADC, DAC12.0 output, and the OA2 input multiplexer on the + and − terminals.
6 P6.7/A7/DAC1/SVSIN bidirectional General-purpose digital I/O, with analog input A7 to the 12-bit ADC, DAC12.1 output, and analog input to the brownout/supply voltage supervisor.
7 VREF+ power_in Output of the positive terminal of the reference voltage in the ADC.
8 XIN input Input port for crystal oscillator XT1; standard or watch crystals can be connected.
9 XOUT output Output terminal of crystal oscillator XT1.
10 VeREF+/DAC0 bidirectional Input for an external reference voltage to the ADC, or the DAC12.0 output.
11 VREF−/VeREF− power_in Negative terminal for the ADC reference voltage, either the internal reference or an externally applied reference voltage.
12 P5.1/S0/A12/DAC1 bidirectional General-purpose digital I/O, LCD segment output S0, analog input A12 to the ADC, and DAC12.1 output; segments S0-S3 are disabled when the LCD charge pump is enabled.
13 P5.0/S1/A13/OA1I1 bidirectional General-purpose digital I/O, LCD segment output S1, analog input A13 to the ADC, and the OA1 input multiplexer; S1 is disabled when the LCD charge pump is enabled.
14 P10.7/S2/A14/OA2I1 bidirectional General-purpose digital I/O, LCD segment output S2, analog input A14 to the ADC, and the OA2 input multiplexer; S2 is disabled when the LCD charge pump is enabled.
15 P10.6/S3/A15 bidirectional General-purpose digital I/O, LCD segment output S3, and analog input A15 to the ADC; S3 is disabled when the LCD charge pump is enabled.
16 P10.5/S4 bidirectional General-purpose digital I/O and LCD segment output S4.
17 P10.4/S5 bidirectional General-purpose digital I/O and LCD segment output S5.
18 P10.3/S6 bidirectional General-purpose digital I/O and LCD segment output S6.
19 P10.2/S7 bidirectional General-purpose digital I/O and LCD segment output S7.
20 P10.1/S8 bidirectional General-purpose digital I/O and LCD segment output S8.
21 P10.0/S9 bidirectional General-purpose digital I/O and LCD segment output S9.
22 P9.7/S10 bidirectional General-purpose digital I/O and LCD segment output S10.
23 P9.6/S11 bidirectional General-purpose digital I/O and LCD segment output S11.
24 P9.5/S12 bidirectional General-purpose digital I/O and LCD segment output S12.
25 P9.4/S13 bidirectional General-purpose digital I/O and LCD segment output S13.
26 P9.3/S14 bidirectional General-purpose digital I/O and LCD segment output S14.
27 P9.2/S15 bidirectional General-purpose digital I/O and LCD segment output S15.
28 P9.1/S16 bidirectional General-purpose digital I/O and LCD segment output S16.
29 P9.0/S17 bidirectional General-purpose digital I/O and LCD segment output S17.
30 P8.7/S18 bidirectional General-purpose digital I/O and LCD segment output S18.
31 P8.6/S19 bidirectional General-purpose digital I/O and LCD segment output S19.
32 P8.5/S20 bidirectional General-purpose digital I/O and LCD segment output S20.
33 P8.4/S21 bidirectional General-purpose digital I/O and LCD segment output S21.
34 P8.3/S22 bidirectional General-purpose digital I/O and LCD segment output S22.
35 P8.2/S23 bidirectional General-purpose digital I/O and LCD segment output S23.
36 P8.1/S24 bidirectional General-purpose digital I/O and LCD segment output S24.
37 P8.0/S25 bidirectional General-purpose digital I/O and LCD segment output S25.
38 P7.7/S26 bidirectional General-purpose digital I/O and LCD segment output S26.
39 P7.6/S27 bidirectional General-purpose digital I/O and LCD segment output S27.
40 P7.5/S28 bidirectional General-purpose digital I/O and LCD segment output S28.
41 P7.4/S29 bidirectional General-purpose digital I/O and LCD segment output S29.
42 P7.3/UCA0CLK/S30 bidirectional General-purpose digital I/O, external clock input or clock output for USCI_A0 in UART or SPI mode, and LCD segment output S30.
43 P7.2/UCA0SOMI/S31 bidirectional General-purpose digital I/O, slave out/master in of USCI_A0 in SPI mode, and LCD segment output S31.
44 P7.1/UCA0SIMO/S32 bidirectional General-purpose digital I/O, slave in/master out of USCI_A0 in SPI mode, and LCD segment output S32.
45 P7.0/UCA0STE/S33 bidirectional General-purpose digital I/O, slave transmit enable of USCI_A0 in SPI mode, and LCD segment output S33.
46 P4.7/UCA0RXD/S34 bidirectional General-purpose digital I/O, receive data input of USCI_A0 in UART or IrDA mode, and LCD segment output S34.
47 P4.6/UCA0TXD/S35 bidirectional General-purpose digital I/O, transmit data output of USCI_A0 in UART or IrDA mode, and LCD segment output S35.
48 P4.5/UCLK1/S36 bidirectional General-purpose digital I/O, external clock input or clock output for USART1 in UART or SPI mode, and LCD segment output S36.
49 P4.4/SOMI1/S37 bidirectional General-purpose digital I/O, slave out/master in of USART1 in SPI mode, and LCD segment output S37.
50 P4.3/SIMO1/S38 bidirectional General-purpose digital I/O, slave in/master out of USART1 in SPI mode, and LCD segment output S38.
51 P4.2/STE1/S39 bidirectional General-purpose digital I/O, slave transmit enable of USART1 in SPI mode, and LCD segment output S39.
52 COM0 output LCD backplane common output COM0 (COM0-3 are used for LCD backplanes).
53 P5.2/COM1 bidirectional General-purpose digital I/O and LCD backplane common output COM1.
54 P5.3/COM2 bidirectional General-purpose digital I/O and LCD backplane common output COM2.
55 P5.4/COM3 bidirectional General-purpose digital I/O and LCD backplane common output COM3.
56 P5.5/R03 bidirectional General-purpose digital I/O and input port of the lowest analog LCD level (V5).
57 P5.6/LCDREF/R13 bidirectional General-purpose digital I/O, external reference voltage input for the regulated LCD voltage, and input port of the third most positive analog LCD level (V4 or V3).
58 P5.7/R23 bidirectional General-purpose digital I/O and input port of the second most positive analog LCD level (V2).
59 LCDCAP/R33 input LCD capacitor connection and input/output port of the most positive analog LCD level (V1).
60 DVCC2 power_in Digital supply voltage, positive terminal.
61 DVSS2 power_in Digital supply voltage, negative terminal.
62 P4.1/URXD1 bidirectional General-purpose digital I/O and receive data input for USART1 in UART mode.
63 P4.0/UTXD1 bidirectional General-purpose digital I/O and transmit data output for USART1 in UART mode.
64 P3.7/TB6 bidirectional General-purpose digital I/O and Timer_B7 CCR6 (capture input CCI6A/CCI6B, compare output Out6).
65 P3.6/TB5 bidirectional General-purpose digital I/O and Timer_B7 CCR5 (capture input CCI5A/CCI5B, compare output Out5).
66 P3.5/TB4 bidirectional General-purpose digital I/O and Timer_B7 CCR4 (capture input CCI4A/CCI4B, compare output Out4).
67 P3.4/TB3 bidirectional General-purpose digital I/O and Timer_B7 CCR3 (capture input CCI3A/CCI3B, compare output Out3).
68 P3.3/UCB0CLK bidirectional General-purpose digital I/O, external clock input or clock output for USCI_B0 in UART or SPI mode.
69 P3.2/UCB0SOMI/UCB0SCL bidirectional General-purpose digital I/O, slave out/master in of USCI_B0 in SPI mode, or I2C clock of USCI_B0 in I2C mode.
70 P3.1/UCB0SIMO/UCB0SDA bidirectional General-purpose digital I/O, slave in/master out of USCI_B0 in SPI mode, or I2C data of USCI_B0 in I2C mode.
71 P3.0/UCB0STE bidirectional General-purpose digital I/O and slave transmit enable of USCI_B0 in SPI mode.
72 P2.7/ADC12CLK/DMAE0 bidirectional General-purpose digital I/O, 12-bit ADC conversion clock, and DMA channel 0 external trigger.
73 P2.6/CAOUT bidirectional General-purpose digital I/O and Comparator_A output.
74 P2.5/UCA0RXD bidirectional General-purpose digital I/O and receive data input of USCI_A0 in UART or IrDA mode.
75 P2.4/UCA0TXD bidirectional General-purpose digital I/O and transmit data output of USCI_A0 in UART or IrDA mode.
76 P2.3/TB2 bidirectional General-purpose digital I/O and Timer_B7 CCR2 (capture input CCI2A/CCI2B, compare output Out2).
77 P2.2/TB1 bidirectional General-purpose digital I/O and Timer_B7 CCR1 (capture input CCI1A/CCI1B, compare output Out1).
78 P2.1/TB0 bidirectional General-purpose digital I/O and Timer_B7 CCR0 (capture input CCI0A/CCI0B, compare output Out0).
79 P2.0/TA2 bidirectional General-purpose digital I/O and Timer_A capture input CCI2A or compare output Out2.
80 P1.7/CA1 bidirectional General-purpose digital I/O and Comparator_A input CA1.
81 P1.6/CA0 bidirectional General-purpose digital I/O and Comparator_A input CA0.
82 P1.5/TACLK/ACLK bidirectional General-purpose digital I/O, Timer_A clock input TACLK, and ACLK output (divided by 1, 2, 4, or 8).
83 P1.4/TBCLK/SMCLK bidirectional General-purpose digital I/O, Timer_B7 input clock TBCLK, and submain system clock SMCLK output.
84 P1.3/TBOUTH/SVSOUT bidirectional General-purpose digital I/O, switches all Timer_B PWM outputs (TB0-TB6) to high impedance, and SVS comparator output.
85 P1.2/TA1 bidirectional General-purpose digital I/O, Timer_A capture input CCI1A, or compare output Out1.
86 P1.1/TA0/MCLK bidirectional General-purpose digital I/O, Timer_A capture input CCI0B, MCLK output, and BSL receive; TA0 is only an input on this pin.
87 P1.0/TA0 bidirectional General-purpose digital I/O, Timer_A capture input CCI0A, compare output Out0, and BSL transmit.
88 XT2OUT output Output terminal of crystal oscillator XT2.
89 XT2IN input Input port for crystal oscillator XT2; only standard crystals can be connected.
90 TDO/TDI bidirectional Test data output port; carries TDO/TDI data output or programming data input.
91 TDI/TCLK input Test data input or test clock input; the device protection fuse is connected to this pin.
92 TMS input Test mode select, used as an input port for device programming and test.
93 TCK input Test clock, the clock input port for device programming and test.
94 RST/NMI input Reset input or nonmaskable interrupt input port.
95 P6.0/A0/OA0I0 bidirectional General-purpose digital I/O, analog input A0 to the 12-bit ADC, and OA0 input multiplexer on the + and − terminals.
96 P6.1/A1/OA0O bidirectional General-purpose digital I/O, analog input A1 to the 12-bit ADC, and OA0 output.
97 P6.2/A2/OA0I1 bidirectional General-purpose digital I/O, analog input A2 to the 12-bit ADC, and OA0 input multiplexer on the + and − terminals.
98 AVSS power_in Analog supply voltage, negative terminal; supplies SVS, brownout, oscillator, Comparator_A, and port 1.
99 DVSS1 power_in Digital supply voltage, negative terminal.
100 AVCC power_in Analog supply voltage, positive terminal; supplies SVS, brownout, oscillator, Comparator_A, and port 1, and must not power up prior to DVCC1/DVCC2.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: MSP430FG4618IPZR
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: msp430fg4618ipzr-etched.step / msp430fg4618ipzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430fg4618ipzr.step / msp430fg4618ipzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (120 pp, sha256 32f5a0cebf27eb7f, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF