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MSP430FE425IPMR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

MSP430FE425IPMR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DVCC power_in Digital supply voltage, positive terminal; it must be within 2.7 V to 3.6 V when the ESP430/SD16 is enabled or flash is being programmed.
2 I1+ input Current 1 positive analog input, internally connected to SD16 channel 0 A0+.
3 I1− input Current 1 negative analog input, internally connected to SD16 channel 0 A0−.
4 I2+ input Current 2 positive analog input, internally connected to SD16 channel 1 A0+.
5 I2− input Current 2 negative analog input, internally connected to SD16 channel 1 A0−.
6 V1+ input Voltage 1 positive analog input, internally connected to SD16 channel 2 A0+.
7 V1− input Voltage 1 negative analog input, internally connected to SD16 channel 2 A0−.
8 XIN input Input port for crystal oscillator XT1; standard or watch crystals can be connected.
9 XOUT output Output terminal of crystal oscillator XT1.
10 VREF power_in Input for an external reference voltage, or internal reference voltage output that can be used as mid-voltage.
11 P2.2/STE0 bidirectional General-purpose digital I/O; slave transmit enable for USART0 in SPI mode.
12 S0 output LCD segment output 0.
13 S1 output LCD segment output 1.
14 S2 output LCD segment output 2.
15 S3 output LCD segment output 3.
16 S4 output LCD segment output 4.
17 S5 output LCD segment output 5.
18 S6 output LCD segment output 6.
19 S7 output LCD segment output 7.
20 S8 output LCD segment output 8.
21 S9 output LCD segment output 9.
22 S10 output LCD segment output 10.
23 S11 output LCD segment output 11.
24 S12 output LCD segment output 12.
25 S13 output LCD segment output 13.
26 S14 output LCD segment output 14.
27 S15 output LCD segment output 15.
28 S16 output LCD segment output 16.
29 S17 output LCD segment output 17.
30 S18 output LCD segment output 18.
31 S19 output LCD segment output 19.
32 S20 output LCD segment output 20.
33 S21 output LCD segment output 21.
34 S22 output LCD segment output 22.
35 S23 output LCD segment output 23.
36 COM0 output Common output; COM0 to COM3 are used for LCD backplanes.
37 COM1 output Common output; COM0 to COM3 are used for LCD backplanes.
38 COM2 output Common output; COM0 to COM3 are used for LCD backplanes.
39 COM3 output Common output; COM0 to COM3 are used for LCD backplanes.
40 R03 input Input port of the fourth (lowest) positive analog LCD level, V5.
41 R13 input Input port of the third most positive analog LCD level, V4 or V3.
42 R23 input Input port of the second most positive analog LCD level, V2.
43 R33 output Output port of the most positive analog LCD level, V1.
44 P2.1/UCLK0/S24 bidirectional General-purpose digital I/O; external clock input for USART0 in UART or SPI mode, or clock output for USART0 in SPI mode; also LCD segment output 24.
45 P2.0/TA2/S25 bidirectional General-purpose digital I/O; Timer_A capture input CCI2A or compare output Out2; also LCD segment output 25.
46 P1.7/SOMI0/S26 bidirectional General-purpose digital I/O; slave out/master in for USART0 in SPI mode; also LCD segment output 26.
47 P1.6/SIMO0/S27 bidirectional General-purpose digital I/O; slave in/master out for USART0 in SPI mode; also LCD segment output 27.
48 P1.5/TACLK/ACLK/S28 bidirectional General-purpose digital I/O; Timer_A and SD16 clock input TACLK or ACLK output divided by 1, 2, 4, or 8; also LCD segment output 28.
49 P1.4/S29 bidirectional General-purpose digital I/O; also LCD segment output 29.
50 P1.3/SVSOUT/S30 bidirectional General-purpose digital I/O; SVS comparator output SVSOUT; also LCD segment output 30.
51 P1.2/TA1/S31 bidirectional General-purpose digital I/O; Timer_A capture inputs CCI1A/CCI1B or compare output Out1; also LCD segment output 31.
52 P1.1/TA0/MCLK bidirectional General-purpose digital I/O; Timer_A capture input CCI0B (TA0 is input only on this pin); MCLK output; BSL receive.
53 P1.0/TA0 bidirectional General-purpose digital I/O; Timer_A capture input CCI0A or compare output Out0; BSL transmit.
54 TDO/TDI bidirectional Test data output port, or programming data input terminal for TDO/TDI data.
55 TDI/TCLK input Test data input or test clock input; the device protection fuse is connected to TDI.
56 TMS input Test mode select; used as an input port for device programming and test.
57 TCK input Test clock; the clock input port for device programming and test.
58 RST/NMI input Reset input or nonmaskable interrupt input port.
59 P2.5/URXD0 bidirectional General-purpose digital I/O; receive data input for USART0 in UART mode.
60 P2.4/UTXD0 bidirectional General-purpose digital I/O; transmit data output for USART0 in UART mode.
61 P2.3/SVSIN bidirectional General-purpose digital I/O; analog input to the brownout and supply voltage supervisor.
62 AVSS power_in Analog supply voltage, negative terminal; supplies SD16, SVS, brownout, oscillator, and LCD resistive divider circuitry.
63 DVSS power_in Digital supply voltage, negative terminal.
64 AVCC power_in Analog supply voltage, positive terminal; supplies SD16, SVS, brownout, oscillator, and LCD resistive divider circuitry; do not power up before DVCC.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: MSP430FE425IPMR
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: msp430fe425ipmr-etched.step / msp430fe425ipmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430fe425ipmr.step / msp430fe425ipmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (67 pp, sha256 9b5a32bc8b742f84, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF