component
MSP430F6779IPEUR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-128(14x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 1d ago |
| viewers | 1d ago |
| msp430f6779ipeur-etched.glb | 1d ago |
| msp430f6779ipeur-etched.step | 1d ago |
| msp430f6779ipeur-hero.glb | 1d ago |
| msp430f6779ipeur-hero.overlay.json | 1d ago |
| msp430f6779ipeur.glb | 1d ago |
| msp430f6779ipeur.kicad_mod | 1d ago |
| msp430f6779ipeur.kicad_sym | 1d ago |
| msp430f6779ipeur.lbr | 1d ago |
| msp430f6779ipeur.step | 1d ago |
| package.json | 1d ago |
| page.json | 1d ago |
| README.md | 1d ago |
MSP430F6779IPEUR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-128(14x20)
MSP430F6779IPEUR from Texas Instruments, in a LQFP-128(14x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | XIN | bidirectional | Input terminal for the crystal oscillator. |
| 2 | XOUT | bidirectional | Output terminal for the crystal oscillator. |
| 3 | AUXVCC3 | power_in | Auxiliary power supply AUXVCC3 for the backup subsystem. |
| 4 | RTCCAP1 | input | External time capture pin 1 for RTC_C. |
| 5 | RTCCAP0 | input | External time capture pin 0 for RTC_C. |
| 6 | P1.5/SMCLK/CB0/A5 | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are SMCLK clock output, Comparator_B input CB0 and 10-bit ADC analog input A5. |
| 7 | P1.4/MCLK/CB1/A4 | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are MCLK clock output, Comparator_B input CB1 and 10-bit ADC analog input A4. |
| 8 | P1.3/ADC10CLK/A3 | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are ADC10_A clock output and analog input A3, and before enabling A3 it must be pulled low by output-low or input with pulldown. |
| 9 | P1.2/ACLK/A2 | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are ACLK clock output and 10-bit ADC analog input A2. |
| 10 | P1.1/TA2.1/VeREF+/A1 | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are Timer TA2 CCR1 capture/compare output, positive ADC reference terminal for an external reference, and analog input A1. |
| 11 | P1.0/TA1.1/VeREF-/A0 | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are Timer TA1 CCR1 capture/compare output, negative ADC reference terminal for an external reference, and analog input A0. |
| 12 | P2.4/PM_TA2.0 | bidirectional | General-purpose digital I/O with port interrupt and mappable secondary function; default mapping is Timer TA2 CCR0 capture/compare. |
| 13 | P2.5/PM_UCB0SOMI/PM_UCB0SCL | bidirectional | General-purpose digital I/O with port interrupt and mappable secondary function; default mapping is eUSCI_B0 SPI slave-out/master-in or I2C clock. |
| 14 | P2.6/PM_UCB0SIMO/PM_UCB0SDA | bidirectional | General-purpose digital I/O with port interrupt and mappable secondary function; default mapping is eUSCI_B0 SPI slave-in/master-out or I2C data. |
| 15 | P2.7/PM_UCB0CLK | bidirectional | General-purpose digital I/O with port interrupt and mappable secondary function; default mapping is eUSCI_B0 clock input/output. |
| 16 | P3.0/PM_UCA0RXD/PM_UCA0SOMI | bidirectional | General-purpose digital I/O with mappable secondary function; default mapping is eUSCI_A0 UART receive data or SPI slave-out/master-in. |
| 17 | P3.1/PM_UCA0TXD/PM_UCA0SIMO | bidirectional | General-purpose digital I/O with mappable secondary function; default mapping is eUSCI_A0 UART transmit data or SPI slave-in/master-out. |
| 18 | P3.2/PM_UCA0CLK | bidirectional | General-purpose digital I/O with mappable secondary function; default mapping is eUSCI_A0 clock input/output. |
| 19 | P3.3/PM_UCA1CLK | bidirectional | General-purpose digital I/O with mappable secondary function; default mapping is eUSCI_A1 clock input/output. |
| 20 | P3.4/PM_UCA1RXD/PM_UCA1SOMI | bidirectional | General-purpose digital I/O with mappable secondary function; default mapping is eUSCI_A1 UART receive data or SPI slave-out/master-in. |
| 21 | P3.5/PM_UCA1TXD/PM_UCA1SIMO | bidirectional | General-purpose digital I/O with mappable secondary function; default mapping is eUSCI_A1 UART transmit data or SPI slave-in/master-out. |
| 22 | COM0 | output | LCD common output COM0 for the LCD backplane. |
| 23 | COM1 | output | LCD common output COM1 for the LCD backplane. |
| 24 | P1.6/COM2 | bidirectional | General-purpose digital I/O with port interrupt; alternate function is LCD common output COM2. |
| 25 | P1.7/COM3 | bidirectional | General-purpose digital I/O with port interrupt; alternate function is LCD common output COM3. |
| 26 | P5.0/COM4 | bidirectional | General-purpose digital I/O; alternate function is LCD common output COM4. |
| 27 | P5.1/COM5 | bidirectional | General-purpose digital I/O; alternate function is LCD common output COM5. |
| 28 | P5.2/COM6 | bidirectional | General-purpose digital I/O; alternate function is LCD common output COM6. |
| 29 | P5.3/COM7 | bidirectional | General-purpose digital I/O; alternate function is LCD common output COM7. |
| 30 | LCDCAP/R33 | bidirectional | LCD capacitor connection and input/output port of the most positive analog LCD voltage (V1); it must be connected to DVSS if not used. |
| 31 | P5.4/SDCLK/R23 | bidirectional | General-purpose digital I/O; alternate functions are SD24_B bit stream clock input/output and the input/output port of the second most positive LCD voltage (V2). |
| 32 | P5.5/SD0DIO/LCDREF/R13 | bidirectional | General-purpose digital I/O; alternate functions are SD24_B converter 0 bit stream data I/O, external reference input for regulated LCD voltage, and the third most positive LCD voltage (V3 or V4) port. |
| 33 | P5.6/SD1DIO/R03 | bidirectional | General-purpose digital I/O; alternate functions are SD24_B converter 1 bit stream data I/O and the lowest analog LCD voltage (V5) port. |
| 34 | P5.7/SD2DIO/CB2 | bidirectional | General-purpose digital I/O; alternate functions are SD24_B converter 2 bit stream data I/O and Comparator_B input CB2. |
| 35 | P6.0/SD3DIO | bidirectional | General-purpose digital I/O; alternate function is SD24_B converter 3 bit stream data I/O. |
| 36 | P3.6/PM_UCA2RXD/PM_UCA2SOMI | bidirectional | General-purpose digital I/O with mappable secondary function; default mapping is eUSCI_A2 UART receive data or SPI slave-out/master-in. |
| 37 | P3.7/PM_UCA2TXD/PM_UCA2SIMO | bidirectional | General-purpose digital I/O with mappable secondary function; default mapping is eUSCI_A2 UART transmit data or SPI slave-in/master-out. |
| 38 | P4.0/PM_UCA2CLK | bidirectional | General-purpose digital I/O with mappable secondary function; default mapping is eUSCI_A2 clock input/output. |
| 39 | P4.1/PM_UCA3RXD/PM_UCA3SOMI | bidirectional | General-purpose digital I/O with mappable secondary function; default mapping is eUSCI_A3 UART receive data or SPI slave-out/master-in. |
| 40 | P4.2/PM_UCA3TXD/PM_UCA3SIMO | bidirectional | General-purpose digital I/O with mappable secondary function; default mapping is eUSCI_A3 UART transmit data or SPI slave-in/master-out. |
| 41 | P4.3/PM_UCA3CLK | bidirectional | General-purpose digital I/O with mappable secondary function; default mapping is eUSCI_A3 clock input/output. |
| 42 | P4.4/PM_UCB1SOMI/PM_UCB1SCL | bidirectional | General-purpose digital I/O with mappable secondary function; default mapping is eUSCI_B1 SPI slave-out/master-in or I2C clock. |
| 43 | P4.5/PM_UCB1SIMO/PM_UCB1SDA | bidirectional | General-purpose digital I/O with mappable secondary function; default mapping is eUSCI_B1 SPI slave-in/master-out or I2C data. |
| 44 | P4.6/PM_UCB1CLK | bidirectional | General-purpose digital I/O with mappable secondary function; default mapping is eUSCI_B1 clock input/output. |
| 45 | P4.7/PM_TA3.0 | bidirectional | General-purpose digital I/O with mappable secondary function; default mapping is Timer TA3 CCR0 capture/compare. |
| 46 | P6.1/SD4DIO/S39 | bidirectional | General-purpose digital I/O; alternate functions are SD24_B converter 4 bit stream data I/O and LCD segment output S39. |
| 47 | P6.2/SD5DIO/S38 | bidirectional | General-purpose digital I/O; alternate functions are SD24_B converter 5 bit stream data I/O and LCD segment output S38. |
| 48 | P6.3/SD6DIO/S37 | bidirectional | General-purpose digital I/O; alternate functions are SD24_B converter 6 bit stream data I/O (not available on F674x and F676x devices) and LCD segment output S37. |
| 49 | P6.4/S36 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S36. |
| 50 | P6.5/S35 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S35. |
| 51 | P6.6/S34 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S34. |
| 52 | P6.7/S33 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S33. |
| 53 | P7.0/S32 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S32. |
| 54 | P7.1/S31 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S31. |
| 55 | P7.2/S30 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S30. |
| 56 | P7.3/S29 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S29. |
| 57 | P7.4/S28 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S28. |
| 58 | P7.5/S27 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S27. |
| 59 | P7.6/S26 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S26. |
| 60 | P7.7/S25 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S25. |
| 61 | P8.0/S24 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S24. |
| 62 | P8.1/S23 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S23. |
| 63 | P8.2/S22 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S22. |
| 64 | P8.3/S21 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S21. |
| 65 | P8.4/S20 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S20. |
| 66 | P8.5/S19 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S19. |
| 67 | P8.6/S18 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S18. |
| 68 | P8.7/S17 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S17. |
| 69 | VDSYS2 | power_in | Digital power supply for the I/Os, which must be connected externally to VDSYS1 for proper device operation with a recommended capacitor CVSYS. |
| 70 | DVSS2 | power_in | Digital ground supply. |
| 71 | P9.0/S16 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S16. |
| 72 | P9.1/S15 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S15. |
| 73 | P9.2/S14 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S14. |
| 74 | P9.3/S13 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S13. |
| 75 | P9.4/S12 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S12. |
| 76 | P9.5/S11 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S11. |
| 77 | P9.6/S10 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S10. |
| 78 | P9.7/S9 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S9. |
| 79 | P10.0/S8 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S8. |
| 80 | P10.1/S7 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S7. |
| 81 | P10.2/S6 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S6. |
| 82 | P10.3/S5 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S5. |
| 83 | P10.4/S4 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S4. |
| 84 | P10.5/S3 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S3. |
| 85 | P10.6/S2 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S2. |
| 86 | P10.7/S1 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S1. |
| 87 | P11.0/S0 | bidirectional | General-purpose digital I/O; alternate function is LCD segment output S0. |
| 88 | P11.1/TA3.1/CB3 | bidirectional | General-purpose digital I/O; alternate functions are Timer TA3 CCR1 capture/compare output and Comparator_B input CB3. |
| 89 | P11.2/TA1.1 | bidirectional | General-purpose digital I/O; alternate function is Timer TA1 CCR1 capture/compare output. |
| 90 | P11.3/TA2.1 | bidirectional | General-purpose digital I/O; alternate function is Timer TA2 CCR1 capture/compare output. |
| 91 | P11.4/CBOUT | bidirectional | General-purpose digital I/O; alternate function is Comparator_B output. |
| 92 | P11.5/TACLK/RTCCLK | bidirectional | General-purpose digital I/O; alternate functions are timer clock input TACLK for TA0 to TA3 and RTCCLK clock output. |
| 93 | P2.0/PM_TA0.0/BSL_TX | bidirectional | General-purpose digital I/O with port interrupt and mappable secondary function; default mapping is Timer TA0 CCR0 capture/compare, and bootloader data transmit. |
| 94 | P2.1/PM_TA0.1/BSL_RX | bidirectional | General-purpose digital I/O with port interrupt and mappable secondary function; default mapping is Timer TA0 CCR1 capture/compare, and bootloader data receive. |
| 95 | P2.2/PM_TA0.2 | bidirectional | General-purpose digital I/O with port interrupt and mappable secondary function; default mapping is Timer TA0 CCR2 capture/compare. |
| 96 | P2.3/PM_TA1.0 | bidirectional | General-purpose digital I/O with port interrupt and mappable secondary function; default mapping is Timer TA1 CCR0 capture/compare. |
| 97 | TEST/SBWTCK | input | Test mode pin that selects digital I/O on the JTAG pins, and serves as the Spy-Bi-Wire input clock. |
| 98 | PJ.0/TDO | bidirectional | General-purpose digital I/O; alternate function is JTAG test data output. |
| 99 | PJ.1/TDI/TCLK | bidirectional | General-purpose digital I/O; alternate function is JTAG test data input or test clock input. |
| 100 | PJ.2/TMS | bidirectional | General-purpose digital I/O; alternate function is JTAG test mode select. |
| 101 | PJ.3/TCK | bidirectional | General-purpose digital I/O; alternate function is JTAG test clock. |
| 102 | RST/NMI/SBWTDIO | bidirectional | Active-low reset input (internal pullup enabled by default when configured as reset), with alternate functions of nonmaskable interrupt input and Spy-Bi-Wire data input/output. |
| 103 | SD0P0 | input | SD24_B positive analog input for converter 0; unused analog input pairs should be shorted and connected to analog ground. |
| 104 | SD0N0 | input | SD24_B negative analog input for converter 0; unused analog input pairs should be shorted and connected to analog ground. |
| 105 | SD1P0 | input | SD24_B positive analog input for converter 1; unused analog input pairs should be shorted and connected to analog ground. |
| 106 | SD1N0 | input | SD24_B negative analog input for converter 1; unused analog input pairs should be shorted and connected to analog ground. |
| 107 | SD2P0 | input | SD24_B positive analog input for converter 2; unused analog input pairs should be shorted and connected to analog ground. |
| 108 | SD2N0 | input | SD24_B negative analog input for converter 2; unused analog input pairs should be shorted and connected to analog ground. |
| 109 | SD3P0 | input | SD24_B positive analog input for converter 3; unused analog input pairs should be shorted and connected to analog ground. |
| 110 | SD3N0 | input | SD24_B negative analog input for converter 3; unused analog input pairs should be shorted and connected to analog ground. |
| 111 | VASYS2 | power_in | Analog power supply selected between AVCC, AUXVCC1 and AUXVCC2; connect the recommended capacitor CVSYS. |
| 112 | AVSS2 | power_in | Analog ground supply. |
| 113 | VREF | power_in | SD24_B external reference voltage input. |
| 114 | SD4P0 | input | SD24_B positive analog input for converter 4 (not available on F674x devices); unused analog input pairs should be shorted and connected to analog ground. |
| 115 | SD4N0 | input | SD24_B negative analog input for converter 4 (not available on F674x devices); unused analog input pairs should be shorted and connected to analog ground. |
| 116 | SD5P0 | input | SD24_B positive analog input for converter 5 (not available on F674x devices); unused analog input pairs should be shorted and connected to analog ground. |
| 117 | SD5N0 | input | SD24_B negative analog input for converter 5 (not available on F674x devices); unused analog input pairs should be shorted and connected to analog ground. |
| 118 | SD6P0 | input | SD24_B positive analog input for converter 6 (not available on F676x and F674x devices); unused analog input pairs should be shorted and connected to analog ground. |
| 119 | SD6N0 | input | SD24_B negative analog input for converter 6 (not available on F676x and F674x devices); unused analog input pairs should be shorted and connected to analog ground. |
| 120 | AVSS1 | power_in | Analog ground supply. |
| 121 | AVCC | power_in | Analog power supply. |
| 122 | VASYS1 | power_in | Analog power supply selected between AVCC, AUXVCC1 and AUXVCC2; connect the recommended capacitor CVSYS. |
| 123 | AUXVCC2 | power_in | Auxiliary power supply AUXVCC2. |
| 124 | AUXVCC1 | power_in | Auxiliary power supply AUXVCC1. |
| 125 | VDSYS1 | power_in | Digital power supply selected between DVCC, AUXVCC1 and AUXVCC2; connect the recommended capacitor CVSYS. |
| 126 | DVCC | power_in | Digital power supply. |
| 127 | DVSS1 | power_in | Digital ground supply. |
| 128 | VCORE | power_out | Regulated core power supply for internal use only, with no external current loading and only the recommended capacitor CVCORE connected. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-128(14x20) |
| Category | Embedded Processors & Controllers |
| Pins | 128 |
CAD (KiCad official)
- Symbol:
MSP430F6779IPEUR - Footprint:
Package_QFP:LQFP-128_14x20mm_P0.5mm - 3D model: LQFP-128(14x20) (KiCad packages3D, STEP)
- 3D model files:
msp430f6779ipeur-etched.step/msp430f6779ipeur-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430f6779ipeur.step/msp430f6779ipeur.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (180 pp, sha256
9c56caf6d0342159, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).