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MSP430F67791AIPZR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSP430F67791AIPZR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

MSP430F67791AIPZR from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SD0P0 input SD24_B positive analog input for converter 0.
2 SD0N0 input SD24_B negative analog input for converter 0.
3 SD1P0 input SD24_B positive analog input for converter 1.
4 SD1N0 input SD24_B negative analog input for converter 1.
5 SD2P0 input SD24_B positive analog input for converter 2.
6 SD2N0 input SD24_B negative analog input for converter 2.
7 SD3P0 input SD24_B positive analog input for converter 3.
8 SD3N0 input SD24_B negative analog input for converter 3.
9 VASYS2 power_in Analog power supply selected between AVCC, AUXVCC1 and AUXVCC2; connect the recommended capacitor value CVSYS.
10 AVSS2 power_in Analog ground supply.
11 VREF power_in SD24_B external reference voltage input.
12 SD4P0 input SD24_B positive analog input for converter 4.
13 SD4N0 input SD24_B negative analog input for converter 4.
14 SD5P0 input SD24_B positive analog input for converter 5.
15 SD5N0 input SD24_B negative analog input for converter 5.
16 SD6P0 input SD24_B positive analog input for converter 6.
17 SD6N0 input SD24_B negative analog input for converter 6.
18 AVSS1 power_in Analog ground supply.
19 AVCC power_in Analog power supply; TI recommends powering AVCC and DVCC from the same source with at most 0.3 V difference.
20 VASYS1 power_in Analog power supply selected between AVCC, AUXVCC1 and AUXVCC2; connect the recommended capacitor value CVSYS.
21 AUXVCC2 power_in Auxiliary power supply AUXVCC2.
22 AUXVCC1 power_in Auxiliary power supply AUXVCC1.
23 VDSYS1 power_in Digital power supply selected between DVCC, AUXVCC1 and AUXVCC2; connect the recommended capacitor value CVSYS. Must be connected externally to VDSYS2.
24 DVCC power_in Digital power supply.
25 DVSS1 power_in Digital ground supply.
26 VCORE power_out Regulated core power supply for internal use only; no external DC loading is possible and it should only be connected to CVCORE.
27 XIN bidirectional Input terminal for the crystal oscillator.
28 XOUT bidirectional Output terminal for the crystal oscillator.
29 AUXVCC3 power_in Auxiliary power supply AUXVCC3 for the backup subsystem.
30 RTCCAP1 input External time capture pin 1 for RTC_C.
31 RTCCAP0 input External time capture pin 0 for RTC_C.
32 P1.5/SMCLK/CB0/A5 bidirectional General-purpose digital I/O with port interrupt, SMCLK clock output, Comparator_B input CB0, and analog input A5 for the 10-bit ADC.
33 P1.4/MCLK/CB1/A4 bidirectional General-purpose digital I/O with port interrupt, MCLK clock output, Comparator_B input CB1, and analog input A4 for the 10-bit ADC.
34 P1.3/ADC10CLK/A3 bidirectional General-purpose digital I/O with port interrupt, ADC10_A clock output, and analog input A3; before enabling the analog function, pull this pin low (output low, or input with pulldown enabled).
35 P1.2/ACLK/A2 bidirectional General-purpose digital I/O with port interrupt, ACLK clock output, and analog input A2 for the 10-bit ADC.
36 P1.1/TA2.1/CBOUT/VeREF+/A1 bidirectional General-purpose digital I/O with port interrupt, Timer TA2 CCR1 capture/compare output, Comparator_B output, positive ADC reference terminal for an external applied reference, and analog input A1.
37 P1.0/TA1.1/VeREF-/A0 bidirectional General-purpose digital I/O with port interrupt, Timer TA1 CCR1 capture/compare output, negative ADC reference terminal for an external applied reference, and analog input A0.
38 COM0 output LCD common output COM0 for the LCD backplane.
39 COM1 output LCD common output COM1 for the LCD backplane.
40 P1.6/COM2 bidirectional General-purpose digital I/O with port interrupt and LCD common output COM2 for the LCD backplane.
41 P1.7/COM3 bidirectional General-purpose digital I/O with port interrupt and LCD common output COM3 for the LCD backplane.
42 P2.0/PM_TA0.0/BSL_TX/COM4 bidirectional General-purpose digital I/O with port interrupt and mappable secondary function; default Timer TA0 CCR0 capture/compare output, bootloader data transmit, and LCD common output COM4.
43 P2.1/PM_TA0.1/BSL_RX/COM5 bidirectional General-purpose digital I/O with port interrupt and mappable secondary function; default Timer TA0 CCR1 capture/compare output, bootloader data receive, and LCD common output COM5.
44 P2.2/PM_TA0.2/COM6 bidirectional General-purpose digital I/O with port interrupt and mappable secondary function; default Timer TA0 CCR2 capture/compare output, and LCD common output COM6.
45 P2.3/PM_TA1.0/COM7 bidirectional General-purpose digital I/O with port interrupt and mappable secondary function; default Timer TA1 CCR0 capture/compare output, and LCD common output COM7.
46 LCDCAP/R33 bidirectional LCD capacitor connection and input/output port of the most positive analog LCD voltage (V1); must be connected to DVSS if not used.
47 P2.4/PM_TA2.0/R23 bidirectional General-purpose digital I/O with port interrupt and mappable secondary function; default Timer TA2 CCR0 capture/compare output, and input/output port of the second most positive analog LCD voltage (V2).
48 P2.5/PM_UCB0SOMI/PM_UCB0SCL/LCDREF/R13 bidirectional General-purpose digital I/O with port interrupt and mappable secondary function; default eUSCI_B0 SPI slave-out/master-in or I2C clock, external reference input for the regulated LCD voltage, and input/output port of the third most positive analog LCD voltage (V3 or V4).
49 P2.6/PM_UCB0SIMO/PM_UCB0SDA/R03 bidirectional General-purpose digital I/O with port interrupt and mappable secondary function; default eUSCI_B0 SPI slave-in/master-out or I2C data, and input/output port of the lowest analog LCD voltage (V5).
50 P2.7/PM_UCB0CLK/CB2 bidirectional General-purpose digital I/O with port interrupt and mappable secondary function; default eUSCI_B0 clock input/output, and Comparator_B input CB2.
51 P3.0/PM_UCA0RXD/PM_UCA0SOMI bidirectional General-purpose digital I/O with mappable secondary function; default eUSCI_A0 UART receive data or SPI slave-out/master-in.
52 P3.1/PM_UCA0TXD/PM_UCA0SIMO/S39 bidirectional General-purpose digital I/O with mappable secondary function; default eUSCI_A0 UART transmit data or SPI slave-in/master-out, and LCD segment output S39.
53 P3.2/PM_UCA0CLK/S38 bidirectional General-purpose digital I/O with mappable secondary function; default eUSCI_A0 clock input/output, and LCD segment output S38.
54 P3.3/PM_UCA1CLK/S37 bidirectional General-purpose digital I/O with mappable secondary function; default eUSCI_A1 clock input/output, and LCD segment output S37.
55 P3.4/PM_UCA1RXD/PM_UCA1SOMI/S36 bidirectional General-purpose digital I/O with mappable secondary function; default eUSCI_A1 UART receive data or SPI slave-out/master-in, and LCD segment output S36.
56 P3.5/PM_UCA1TXD/PM_UCA1SIMO/S35 bidirectional General-purpose digital I/O with mappable secondary function; default eUSCI_A1 UART transmit data or SPI slave-in/master-out, and LCD segment output S35.
57 P3.6/PM_UCA2RXD/PM_UCA2SOMI/S34 bidirectional General-purpose digital I/O with mappable secondary function; default eUSCI_A2 UART receive data or SPI slave-out/master-in, and LCD segment output S34.
58 P3.7/PM_UCA2TXD/PM_UCA2SIMO/S33 bidirectional General-purpose digital I/O with mappable secondary function; default eUSCI_A2 UART transmit data or SPI slave-in/master-out, and LCD segment output S33.
59 P4.0/PM_UCA2CLK/S32 bidirectional General-purpose digital I/O with mappable secondary function; default eUSCI_A2 clock input/output, and LCD segment output S32.
60 P4.1/PM_UCA3RXD/PM_UCA3SOMI/S31 bidirectional General-purpose digital I/O with mappable secondary function; default eUSCI_A3 UART receive data or SPI slave-out/master-in, and LCD segment output S31.
61 P4.2/PM_UCA3TXD/PM_UCA3SIMO/S30 bidirectional General-purpose digital I/O with mappable secondary function; default eUSCI_A3 UART transmit data or SPI slave-in/master-out, and LCD segment output S30.
62 P4.3/PM_UCA3CLK/S29 bidirectional General-purpose digital I/O with mappable secondary function; default eUSCI_A3 clock input/output, and LCD segment output S29.
63 P4.4/PM_UCB1SOMI/PM_UCB1SCL/S28 bidirectional General-purpose digital I/O with mappable secondary function; default eUSCI_B1 SPI slave-out/master-in or I2C clock, and LCD segment output S28.
64 P4.5/PM_UCB1SIMO/PM_UCB1SDA/S27 bidirectional General-purpose digital I/O with mappable secondary function; default eUSCI_B1 SPI slave-in/master-out or I2C data, and LCD segment output S27.
65 P4.6/PM_UCB1CLK/S26 bidirectional General-purpose digital I/O with mappable secondary function; default eUSCI_B1 clock input/output, and LCD segment output S26.
66 P4.7/PM_TA3.0/S25 bidirectional General-purpose digital I/O with mappable secondary function; default Timer TA3 CCR0 capture/compare output, and LCD segment output S25.
67 P5.0/SDCLK/S24 bidirectional General-purpose digital I/O with SD24_B bit-stream clock input/output and LCD segment output S24.
68 P5.1/PM_SD0DIO/S23 bidirectional General-purpose digital I/O with default SD24_B converter 0 bit-stream data input/output and LCD segment output S23.
69 P5.2/PM_SD1DIO/S22 bidirectional General-purpose digital I/O with default SD24_B converter 1 bit-stream data input/output and LCD segment output S22.
70 P5.3/PM_SD2DIO/S21 bidirectional General-purpose digital I/O with default SD24_B converter 2 bit-stream data input/output and LCD segment output S21.
71 P5.4/PM_SD3DIO/S20 bidirectional General-purpose digital I/O with default SD24_B converter 3 bit-stream data input/output and LCD segment output S20.
72 P5.5/PM_SD4DIO/S19 bidirectional General-purpose digital I/O with default SD24_B converter 4 bit-stream data input/output and LCD segment output S19.
73 P5.6/PM_SD5DIO/S18 bidirectional General-purpose digital I/O with default SD24_B converter 5 bit-stream data input/output and LCD segment output S18.
74 P5.7/PM_SD6DIO/S17 bidirectional General-purpose digital I/O with default SD24_B converter 6 bit-stream data input/output and LCD segment output S17.
75 VDSYS2 power_in Digital power supply for I/Os; must be connected externally to VDSYS1.
76 DVSS2 power_in Digital ground supply.
77 P6.0/S16 bidirectional General-purpose digital I/O with LCD segment output S16.
78 P6.1/S15 bidirectional General-purpose digital I/O with LCD segment output S15.
79 P6.2/S14 bidirectional General-purpose digital I/O with LCD segment output S14.
80 P6.3/S13 bidirectional General-purpose digital I/O with LCD segment output S13.
81 P6.4/S12 bidirectional General-purpose digital I/O with LCD segment output S12.
82 P6.5/S11 bidirectional General-purpose digital I/O with LCD segment output S11.
83 P6.6/S10 bidirectional General-purpose digital I/O with LCD segment output S10.
84 P6.7/S9 bidirectional General-purpose digital I/O with LCD segment output S9.
85 P7.0/S8 bidirectional General-purpose digital I/O with LCD segment output S8.
86 P7.1/S7 bidirectional General-purpose digital I/O with LCD segment output S7.
87 P7.2/S6 bidirectional General-purpose digital I/O with LCD segment output S6.
88 P7.3/S5 bidirectional General-purpose digital I/O with LCD segment output S5.
89 P7.4/S4 bidirectional General-purpose digital I/O with LCD segment output S4.
90 P7.5/S3 bidirectional General-purpose digital I/O with LCD segment output S3.
91 P7.6/S2 bidirectional General-purpose digital I/O with LCD segment output S2.
92 P7.7/S1 bidirectional General-purpose digital I/O with LCD segment output S1.
93 P8.0/S0 bidirectional General-purpose digital I/O with LCD segment output S0.
94 P8.1/TACLK/RTCCLK/CB3 bidirectional General-purpose digital I/O with Timer clock input TACLK for TA0 to TA3, RTCCLK clock output, and Comparator_B input CB3.
95 TEST/SBWTCK input Test mode pin that selects digital I/O on the JTAG pins, and Spy-Bi-Wire input clock; it always has an internal pulldown enabled.
96 PJ.0/TDO bidirectional General-purpose digital I/O and JTAG test data output (TDO).
97 PJ.1/TDI/TCLK bidirectional General-purpose digital I/O and JTAG test data input or test clock input (TCLK).
98 PJ.2/TMS bidirectional General-purpose digital I/O and JTAG test mode select (TMS).
99 PJ.3/TCK bidirectional General-purpose digital I/O and JTAG test clock (TCK).
100 RST/NMI/SBWTDIO bidirectional Active-low reset input (internal pullup enabled by default when configured as reset), nonmaskable interrupt input, and Spy-By-Wire data input/output.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: MSP430F67791AIPZR
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: msp430f67791aipzr-etched.step / msp430f67791aipzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430f67791aipzr.step / msp430f67791aipzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (187 pp, sha256 fab731e7ae1f3a44, retrieved 2026-10-12, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF