# MSP430F67641AIPNR

**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)

MSP430F67641AIPNR from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SD0P0 | input | SD24_B converter 0 positive differential analog input (AVCC-powered, reset state OFF) with a protection diode to VCC and a diode current limit of 2 mA. |
| 2 | SD0N0 | input | SD24_B converter 0 negative differential analog input (AVCC-powered, reset state OFF) with a protection diode to VCC and a diode current limit of 2 mA. |
| 3 | SD1P0 | input | SD24_B converter 1 positive differential analog input (AVCC-powered, reset state OFF) with a protection diode to VCC and a diode current limit of 2 mA. |
| 4 | SD1N0 | input | SD24_B converter 1 negative differential analog input (AVCC-powered, reset state OFF) with a protection diode to VCC and a diode current limit of 2 mA. |
| 5 | SD2P0 | input | SD24_B converter 2 positive differential analog input (AVCC-powered, reset state OFF) with a protection diode to VCC and a diode current limit of 2 mA. |
| 6 | SD2N0 | input | SD24_B converter 2 negative differential analog input (AVCC-powered, reset state OFF) with a protection diode to VCC and a diode current limit of 2 mA. |
| 7 | VREF | power_in | Analog voltage-reference pin (AVCC-powered, reset state OFF) listed as an analog input in the pin attribute table. |
| 8 | AVSS | power_in | Analog ground; AVSS is held at 0 V and must equal DVSS (VSS = VAVSS = VDVSS). |
| 9 | AVCC | power_in | Analog supply; TI recommends powering AVCC and DVCC from the same source with at most 0.3 V difference, within the 1.8 V to 3.6 V VCC range. |
| 10 | VASYS | power_in | Analog system supply pin per the pin attribute table; the provided excerpt gives no further electrical limit for this pin. |
| 11 | P1.0/PM_TA0.0/VeREF-/A2 | bidirectional | General-purpose digital I/O from DVCC with port interrupt, default secondary Timer_A TA0.0 function, VeREF- external ADC reference input and ADC A2 analog input; reset state OFF. |
| 12 | P1.1/PM_TA0.1/VeREF+/A1 | bidirectional | General-purpose digital I/O from DVCC with port interrupt, default secondary Timer_A TA0.1 function, VeREF+ external ADC reference input and ADC A1 analog input; reset state OFF. |
| 13 | P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0 | bidirectional | General-purpose digital I/O from DVCC with port interrupt, eUSCI_A0 UART receive or SPI slave-out secondary function, and ADC A0 analog input; reset state OFF. |
| 14 | P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03 | bidirectional | General-purpose digital I/O from DVCC with port interrupt, eUSCI_A0 UART transmit or SPI slave-in secondary function, and R03 LCD analog pin; reset state OFF. |
| 15 | AUXVCC2 | power_in | Auxiliary supply 2; maximum load current is 20 mA for core and IO and 5 mA for analog modules. |
| 16 | AUXVCC1 | power_in | Auxiliary supply 1; maximum load current is 20 mA for core and IO and 5 mA for analog modules. |
| 17 | VDSYS | power_in | System supply pin that must be connected externally on the board for proper device operation. |
| 18 | DVCC | power_in | Digital supply, 1.8 V to 3.6 V, with maximum load current of 20 mA for core and IO; TI recommends DVCC and AVCC from the same source. |
| 19 | DVSS | power_in | Digital ground; DVSS is held at 0 V and must equal AVSS (VSS = VDVSS = VAVSS). |
| 20 | VCORE | power_out | Internal core-voltage output for internal device use only; no external DC load or voltage should be applied, and a 470 nF capacitor is recommended. |
| 21 | XIN | input | Input terminal for the 32.768 kHz crystal oscillator (DVCC-powered LVCMOS, reset state OFF); unused XIN connects to DVSS. |
| 22 | XOUT | output | Output terminal for the crystal oscillator (DVCC-powered LVCMOS, reset state OFF); left open when unused. |
| 23 | AUXVCC3 | power_in | Dedicated backup-subsystem supply powering the low-frequency oscillator XT1, the RTC module and backup RAM during LPM3.5. |
| 24 | P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13 | bidirectional | General-purpose digital I/O from DVCC with port interrupt, eUSCI_A1 UART receive or SPI slave-out secondary function, and LCD reference/R13 analog pin; reset state OFF. |
| 25 | P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23 | bidirectional | General-purpose digital I/O from DVCC with port interrupt, eUSCI_A1 UART transmit or SPI slave-in secondary function, and R23 LCD analog pin; reset state OFF. |
| 26 | LCDCAP/R33 | bidirectional | LCD capacitor/R33 analog pin (AVCC-powered, reset state OFF); it must be connected to DVSS if not used. |
| 27 | COM0 | output | LCD common driver output COM0 (DVCC-powered, reset state OFF). |
| 28 | COM1 | output | LCD common driver output COM1 (DVCC-powered, reset state OFF). |
| 29 | COM2 | output | LCD common driver output COM2 (DVCC-powered, reset state OFF). |
| 30 | COM3 | output | LCD common driver output COM3 (DVCC-powered, reset state OFF). |
| 31 | P1.6/PM_UCA0CLK/COM4 | bidirectional | General-purpose digital I/O from DVCC with port interrupt, eUSCI_A0 clock input/output secondary function, and LCD common output COM4; reset state OFF. |
| 32 | P1.7/PM_UCB0CLK/COM5 | bidirectional | General-purpose digital I/O from DVCC with port interrupt, eUSCI_B0 clock input/output secondary function, and LCD common output COM5; reset state OFF. |
| 33 | P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6/S39 | bidirectional | General-purpose digital I/O from DVCC with eUSCI_B0 SPI slave-out or I2C clock secondary function, LCD common output COM6 and segment S39; reset state OFF. |
| 34 | P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7/S38 | bidirectional | General-purpose digital I/O from DVCC with eUSCI_B0 SPI slave-in or I2C data secondary function, LCD common output COM7 and segment S38; reset state OFF. |
| 35 | P2.2/PM_UCA2RXD/PM_UCA2SOMI/S37 | bidirectional | General-purpose digital I/O from DVCC with port interrupt, eUSCI_A2 UART receive or SPI slave-out secondary function, and LCD segment S37; reset state OFF. |
| 36 | P2.3/PM_UCA2TXD/PM_UCA2SIMO/S36 | bidirectional | General-purpose digital I/O from DVCC with port interrupt, eUSCI_A2 UART transmit or SPI slave-in secondary function, and LCD segment S36; reset state OFF. |
| 37 | P2.4/PM_UCA1CLK/S35 | bidirectional | General-purpose digital I/O from DVCC with port interrupt, eUSCI_A1 clock secondary function, and LCD segment S35; reset state OFF. |
| 38 | P2.5/PM_UCA2CLK/S34 | bidirectional | General-purpose digital I/O from DVCC with port interrupt, eUSCI_A2 clock secondary function, and LCD segment S34; reset state OFF. |
| 39 | P2.6/PM_TA1.0/S33 | bidirectional | General-purpose digital I/O from DVCC with port interrupt, Timer_A TA1.0 secondary function, and LCD segment S33; reset state OFF. |
| 40 | P2.7/PM_TA1.1/S32 | bidirectional | General-purpose digital I/O from DVCC with port interrupt, Timer_A TA1.1 secondary function, and LCD segment S32; reset state OFF. |
| 41 | P3.0/PM_TA2.0/S31/BSL_TX | bidirectional | General-purpose digital I/O from DVCC with Timer_A TA2.0 secondary function, LCD segment S31 and bootloader transmit output BSL_TX; reset state OFF. |
| 42 | P3.1/PM_TA2.1/S30/BSL_RX | bidirectional | General-purpose digital I/O from DVCC with Timer_A TA2.1 secondary function, LCD segment S30 and bootloader receive input BSL_RX; reset state OFF. |
| 43 | P3.2/PM_TACLK/PM_RTCCLK/S29 | bidirectional | General-purpose digital I/O from DVCC with Timer_A TACLK input or RTC clock output secondary function, and LCD segment S29; reset state OFF. |
| 44 | P3.3/PM_TA0.2/S28 | bidirectional | General-purpose digital I/O from DVCC with Timer_A TA0.2 secondary function and LCD segment S28; reset state OFF. |
| 45 | P3.4/PM_SDCLK/S27 | bidirectional | General-purpose digital I/O from DVCC with SD24_B bit-stream clock input/output secondary function and LCD segment S27; reset state OFF. |
| 46 | P3.5/PM_SD0DIO/S26 | bidirectional | General-purpose digital I/O from DVCC with SD24_B converter 0 bit-stream data secondary function and LCD segment S26; reset state OFF. |
| 47 | P3.6/PM_SD1DIO/S25 | bidirectional | General-purpose digital I/O from DVCC with SD24_B converter 1 bit-stream data secondary function and LCD segment S25; reset state OFF. |
| 48 | P3.7/PM_SD2DIO/S24 | bidirectional | General-purpose digital I/O from DVCC with SD24_B converter 2 bit-stream data secondary function and LCD segment S24; reset state OFF. |
| 49 | P4.0/S23 | bidirectional | General-purpose digital I/O from DVCC that can be switched to LCD segment S23; reset state OFF. |
| 50 | P4.1/S22 | bidirectional | General-purpose digital I/O from DVCC that can be switched to LCD segment S22; reset state OFF. |
| 51 | P4.2/S21 | bidirectional | General-purpose digital I/O from DVCC that can be switched to LCD segment S21; reset state OFF. |
| 52 | P4.3/S20 | bidirectional | General-purpose digital I/O from DVCC that can be switched to LCD segment S20; reset state OFF. |
| 53 | P4.4/S19 | bidirectional | General-purpose digital I/O from DVCC that can be switched to LCD segment S19; reset state OFF. |
| 54 | P4.5/S18 | bidirectional | General-purpose digital I/O from DVCC that can be switched to LCD segment S18; reset state OFF. |
| 55 | P4.6/S17 | bidirectional | General-purpose digital I/O from DVCC that can be switched to LCD segment S17; reset state OFF. |
| 56 | P4.7/S16 | bidirectional | General-purpose digital I/O from DVCC that can be switched to LCD segment S16; reset state OFF. |
| 57 | P5.0/S15 | bidirectional | General-purpose digital I/O from DVCC that can be switched to LCD segment S15; reset state OFF. |
| 58 | P5.1/S14 | bidirectional | General-purpose digital I/O from DVCC that can be switched to LCD segment S14; reset state OFF. |
| 59 | DVSYS | power_in | System supply pin that must be connected externally on the board for proper device operation. |
| 60 | DVSS | power_in | Digital ground; DVSS is held at 0 V and must equal AVSS (VSS = VDVSS = VAVSS). |
| 61 | P5.2/S13 | bidirectional | General-purpose digital I/O from DVCC that can be switched to LCD segment S13; reset state OFF. |
| 62 | P5.3/S12 | bidirectional | General-purpose digital I/O from DVCC that can be switched to LCD segment S12; reset state OFF. |
| 63 | P5.4/S11 | bidirectional | General-purpose digital I/O from DVCC that can be switched to LCD segment S11; reset state OFF. |
| 64 | P5.5/S10 | bidirectional | General-purpose digital I/O from DVCC that can be switched to LCD segment S10; reset state OFF. |
| 65 | P5.6/S9 | bidirectional | General-purpose digital I/O from DVCC that can be switched to LCD segment S9; reset state OFF. |
| 66 | P5.7/S8 | bidirectional | General-purpose digital I/O from DVCC that can be switched to LCD segment S8; reset state OFF. |
| 67 | P6.0/S7 | bidirectional | General-purpose digital I/O from DVCC that can be switched to LCD segment S7; reset state OFF. |
| 68 | P6.1/S6 | bidirectional | General-purpose digital I/O from DVCC that can be switched to LCD segment S6; reset state OFF. |
| 69 | P6.2/S5 | bidirectional | General-purpose digital I/O from DVCC that can be switched to LCD segment S5; reset state OFF. |
| 70 | P6.3/S4 | bidirectional | General-purpose digital I/O from DVCC that can be switched to LCD segment S4; reset state OFF. |
| 71 | P6.4/S3 | bidirectional | General-purpose digital I/O from DVCC that can be switched to LCD segment S3; reset state OFF. |
| 72 | P6.5/S2 | bidirectional | General-purpose digital I/O from DVCC that can be switched to LCD segment S2; reset state OFF. |
| 73 | P6.6/S1 | bidirectional | General-purpose digital I/O from DVCC that can be switched to LCD segment S1; reset state OFF. |
| 74 | P6.7/S0 | bidirectional | General-purpose digital I/O from DVCC that can be switched to LCD segment S0; reset state OFF. |
| 75 | TEST/SBWTCK | input | TEST is the test-mode pin that selects digital I/O on the JTAG pins and always has an internal pulldown enabled; SBWTCK is the Spy-Bi-Wire clock input. |
| 76 | PJ.0/SMCLK/TDO | bidirectional | JTAG-shared general-purpose I/O from DVCC with SMCLK output and TDO test-data output; unused pins are switched to output direction and left open when used as JTAG pins. |
| 77 | PJ.1/MCLK/TDI/TCLK | bidirectional | JTAG-shared general-purpose I/O from DVCC with MCLK output and TDI/TCLK test-data or test-clock input; unused pins are switched to output direction and left open when used as JTAG pins. |
| 78 | PJ.2/ADC10CLK/TMS | bidirectional | JTAG-shared general-purpose I/O from DVCC with ADC10CLK output and TMS test-mode-select input; unused pins are switched to output direction and left open when used as JTAG pins. |
| 79 | PJ.3/ACLK/TCK | bidirectional | JTAG-shared general-purpose I/O from DVCC with ACLK output and TCK test-clock input; unused pins are switched to output direction and left open when used as JTAG pins. |
| 80 | RST/NMI/SBWTDIO | bidirectional | Active-low reset input with internal pullup enabled at reset (reset state PU), NMI nonmaskable interrupt input, and SBWTDIO Spy-Bi-Wire data input/output. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-80(12x12) |
| Category | Embedded Processors & Controllers |
| Pins | 80 |

## CAD (KiCad official)

- Symbol: `MSP430F67641AIPNR`
- Footprint: `Package_QFP:LQFP-80_12x12mm_P0.5mm`
- 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
- 3D model files: `msp430f67641aipnr-etched.step` / `msp430f67641aipnr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430f67641aipnr.step` / `msp430f67641aipnr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430f67641a) (161 pp, sha256 `4f4b60167e8688ea`, retrieved 2026-10-11, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/msp430f67641aipnr-datasheet.pdf)