component
MSP430F6736IPN
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430F6736IPN
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)
MSP430F6736IPN from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SD0P0 | input | SD24_B positive analog input for converter 0. |
| 2 | SD0N0 | input | SD24_B negative analog input for converter 0. |
| 3 | SD1P0 | input | SD24_B positive analog input for converter 1. |
| 4 | SD1N0 | input | SD24_B negative analog input for converter 1. |
| 5 | SD2P0 | input | SD24_B positive analog input for converter 2; not available on F672x devices. |
| 6 | SD2N0 | input | SD24_B negative analog input for converter 2; not available on F672x devices. |
| 7 | VREF | power_in | SD24_B external reference voltage. |
| 8 | AVSS | power_in | Analog ground supply. |
| 9 | AVCC | power_in | Analog power supply. |
| 10 | VASYS | power_in | Analog power supply selected between AVCC, AUXVCC1, AUXVCC2; connect recommended capacitor CVSYS. |
| 11 | P1.0/PM_TA0.0/VeREF-/A2 | bidirectional | General-purpose digital I/O with port interrupt and mappable secondary function; default: Timer TA0 CCR0 capture input or compare output; VeREF- for ADC reference; analog input A2. |
| 12 | P1.1/PM_TA0.1/VeREF+/A1 | bidirectional | General-purpose digital I/O with port interrupt and mappable secondary function; default: Timer TA0 CCR1 capture input or compare output; VeREF+ for ADC reference; analog input A1. |
| 13 | P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0 | bidirectional | General-purpose digital I/O with port interrupt and mappable secondary function; default: eUSCI_A0 UART receive data or SPI slave out/master in; analog input A0. |
| 14 | P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03 | bidirectional | General-purpose digital I/O with port interrupt and mappable secondary function; default: eUSCI_A0 UART transmit data or SPI slave in/master out; LCD voltage port R03. |
| 15 | AUXVCC2 | power_in | Auxiliary power supply AUXVCC2. |
| 16 | AUXVCC1 | power_in | Auxiliary power supply AUXVCC1. |
| 17 | VDSYS | power_in | Digital power supply selected between DVCC, AUXVCC1, AUXVCC2; must be connected externally for proper device operation; connect recommended capacitor CVSYS. |
| 18 | DVCC | power_in | Digital power supply. |
| 19 | DVSS | power_in | Digital ground supply. |
| 20 | VCORE | power_in | Regulated core power supply for internal use only; no external current loading; connect recommended capacitor CVCORE. |
| 21 | XIN | input | Input terminal for crystal oscillator. |
| 22 | XOUT | output | Output terminal for crystal oscillator. |
| 23 | AUXVCC3 | power_in | Auxiliary power supply AUXVCC3 for backup subsystem. |
| 24 | P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13 | bidirectional | General-purpose digital I/O with port interrupt and mappable secondary function; default: eUSCI_A1 UART receive or SPI slave out/master in; external LCD reference voltage; LCD voltage port R13. |
| 25 | P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23 | bidirectional | General-purpose digital I/O with port interrupt and mappable secondary function; default: eUSCI_A1 UART transmit or SPI slave in/master out; LCD voltage port R23. |
| 26 | LCDCAP/R33 | bidirectional | LCD capacitor connection; LCD voltage port R33; must be connected to DVSS if not used. |
| 27 | COM0 | output | LCD common output COM0 for LCD backplane. |
| 28 | COM1 | output | LCD common output COM1 for LCD backplane. |
| 29 | COM2 | output | LCD common output COM2 for LCD backplane. |
| 30 | COM3 | output | LCD common output COM3 for LCD backplane. |
| 31 | P1.6/PM_UCA0CLK/COM4 | bidirectional | General-purpose digital I/O with port interrupt and mappable secondary function; default: eUSCI_A0 clock input/output; LCD common output COM4. |
| 32 | P1.7/PM_UCB0CLK/COM5 | bidirectional | General-purpose digital I/O with port interrupt and mappable secondary function; default: eUSCI_B0 clock input/output; LCD common output COM5. |
| 33 | P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6/S39 | bidirectional | General-purpose digital I/O with port interrupt and mappable secondary function; default: eUSCI_B0 SPI slave out/master in or I2C clock; LCD common output COM6; LCD segment S39. |
| 34 | P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7/S38 | bidirectional | General-purpose digital I/O with port interrupt and mappable secondary function; default: eUSCI_B0 SPI slave in/master out or I2C data; LCD common output COM7; LCD segment S38. |
| 35 | P2.2/PM_UCA2RXD/PM_UCA2SOMI/S37 | bidirectional | General-purpose digital I/O with port interrupt and mappable secondary function; default: eUSCI_A2 UART receive or SPI slave out/master in; LCD segment S37. |
| 36 | P2.3/PM_UCA2TXD/PM_UCA2SIMO/S36 | bidirectional | General-purpose digital I/O with port interrupt and mappable secondary function; default: eUSCI_A2 UART transmit or SPI slave in/master out; LCD segment S36. |
| 37 | P2.4/PM_UCA1CLK/S35 | bidirectional | General-purpose digital I/O with port interrupt and mappable secondary function; default: eUSCI_A1 clock input/output; LCD segment S35. |
| 38 | P2.5/PM_UCA2CLK/S34 | bidirectional | General-purpose digital I/O with port interrupt and mappable secondary function; default: eUSCI_A2 clock input/output; LCD segment S34. |
| 39 | P2.6/PM_TA1.0/S33 | bidirectional | General-purpose digital I/O with port interrupt and mappable secondary function; default: Timer TA1 CCR0 capture input or compare output; LCD segment S33. |
| 40 | P2.7/PM_TA1.1/S32 | bidirectional | General-purpose digital I/O with port interrupt and mappable secondary function; default: Timer TA1 CCR1 capture input or compare output; LCD segment S32. |
| 41 | P3.0/PM_TA2.0/S31/BSL_TX | bidirectional | General-purpose digital I/O with mappable secondary function; default: Timer TA2 CCR0 capture input or compare output; LCD segment S31; bootloader data transmit. |
| 42 | P3.1/PM_TA2.1/S30/BSL_RX | bidirectional | General-purpose digital I/O with mappable secondary function; default: Timer TA2 CCR1 capture input or compare output; LCD segment S30; bootloader data receive. |
| 43 | P3.2/PM_TACLK/PM_RTCCLK/S29 | bidirectional | General-purpose digital I/O with mappable secondary function; default: timer clock input TACLK or RTC_C clock output; LCD segment S29. |
| 44 | P3.3/PM_TA0.2/S28 | bidirectional | General-purpose digital I/O with mappable secondary function; default: Timer TA0 CCR2 capture input or compare output; LCD segment S28. |
| 45 | P3.4/PM_SDCLK/S27 | bidirectional | General-purpose digital I/O with mappable secondary function; default: SD24_B bitstream clock input/output; LCD segment S27. |
| 46 | P3.5/PM_SD0DIO/S26 | bidirectional | General-purpose digital I/O with mappable secondary function; default: SD24_B converter-0 bitstream data input/output; LCD segment S26. |
| 47 | P3.6/PM_SD1DIO/S25 | bidirectional | General-purpose digital I/O with mappable secondary function; default: SD24_B converter-1 bitstream data input/output; LCD segment S25. |
| 48 | P3.7/PM_SD2DIO/S24 | bidirectional | General-purpose digital I/O with mappable secondary function; default: SD24_B converter-2 bitstream data input/output (not available on F672x); LCD segment S24. |
| 49 | P4.0/S23 | bidirectional | General-purpose digital I/O; LCD segment S23. |
| 50 | P4.1/S22 | bidirectional | General-purpose digital I/O; LCD segment S22. |
| 51 | P4.2/S21 | bidirectional | General-purpose digital I/O; LCD segment S21. |
| 52 | P4.3/S20 | bidirectional | General-purpose digital I/O; LCD segment S20. |
| 53 | P4.4/S19 | bidirectional | General-purpose digital I/O; LCD segment S19. |
| 54 | P4.5/S18 | bidirectional | General-purpose digital I/O; LCD segment S18. |
| 55 | P4.6/S17 | bidirectional | General-purpose digital I/O; LCD segment S17. |
| 56 | P4.7/S16 | bidirectional | General-purpose digital I/O; LCD segment S16. |
| 57 | P5.0/S15 | bidirectional | General-purpose digital I/O; LCD segment S15. |
| 58 | P5.1/S14 | bidirectional | General-purpose digital I/O; LCD segment S14. |
| 59 | DVSYS | power_in | Digital power supply for I/Os; must be connected externally for proper device operation. |
| 60 | DVSS | power_in | Digital ground supply. |
| 61 | P5.2/S13 | bidirectional | General-purpose digital I/O; LCD segment S13. |
| 62 | P5.3/S12 | bidirectional | General-purpose digital I/O; LCD segment S12. |
| 63 | P5.4/S11 | bidirectional | General-purpose digital I/O; LCD segment S11. |
| 64 | P5.5/S10 | bidirectional | General-purpose digital I/O; LCD segment S10. |
| 65 | P5.6/S9 | bidirectional | General-purpose digital I/O; LCD segment S9. |
| 66 | P5.7/S8 | bidirectional | General-purpose digital I/O; LCD segment S8. |
| 67 | P6.0/S7 | bidirectional | General-purpose digital I/O; LCD segment S7. |
| 68 | P6.1/S6 | bidirectional | General-purpose digital I/O; LCD segment S6. |
| 69 | P6.2/S5 | bidirectional | General-purpose digital I/O; LCD segment S5. |
| 70 | P6.3/S4 | bidirectional | General-purpose digital I/O; LCD segment S4. |
| 71 | P6.4/S3 | bidirectional | General-purpose digital I/O; LCD segment S3. |
| 72 | P6.5/S2 | bidirectional | General-purpose digital I/O; LCD segment S2. |
| 73 | P6.6/S1 | bidirectional | General-purpose digital I/O; LCD segment S1. |
| 74 | P6.7/S0 | bidirectional | General-purpose digital I/O; LCD segment S0. |
| 75 | TEST/SBWTCK | input | Test mode pin to select digital I/O on JTAG pins; Spy-Bi-Wire input clock. |
| 76 | PJ.0/SMCLK/TDO | bidirectional | General-purpose digital I/O; SMCLK clock output; JTAG test data output. |
| 77 | PJ.1/MCLK/TDI/TCLK | bidirectional | General-purpose digital I/O; MCLK clock output; JTAG test data input or test clock input. |
| 78 | PJ.2/ADC10CLK/TMS | bidirectional | General-purpose digital I/O; ADC10_A clock output; JTAG test mode select. |
| 79 | PJ.3/ACLK/TCK | bidirectional | General-purpose digital I/O; ACLK clock output; JTAG test clock. |
| 80 | RST/NMI/SBWTDIO | bidirectional | Reset input active low with internal pullup resistor enabled by default; nonmaskable interrupt input; Spy-Bi-Wire data input/output. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-80(12x12) |
| Category | Embedded Processors & Controllers |
| Pins | 80 |
CAD (KiCad official)
- Symbol:
MSP430F6736IPN - Footprint:
Package_QFP:LQFP-80_12x12mm_P0.5mm - 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
- 3D model files:
msp430f6736ipn-etched.step/msp430f6736ipn-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430f6736ipn.step/msp430f6736ipn.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (154 pp, sha256
3f8f4b9a2dc07004, retrieved 2026-10-06, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).