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MSP430F6723IPNR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSP430F6723IPNR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)

MSP430F6723IPNR from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SD0P0 input SD24_B positive analog input for converter 0.
2 SD0N0 input SD24_B negative analog input for converter 0; short unused analog input pairs and connect them to analog ground.
3 SD1P0 input SD24_B positive analog input for converter 1.
4 SD1N0 input SD24_B negative analog input for converter 1; short unused analog input pairs and connect them to analog ground.
5 NC unconnected Not connected on F672x devices (SD2P0 is available only on F673x devices).
6 NC unconnected Not connected on F672x devices (SD2N0 is available only on F673x devices).
7 VREF power_in SD24_B external reference voltage input.
8 AVSS power_in Analog ground supply.
9 AVCC power_in Analog power supply.
10 VASYS power_in Analog power supply selected between AVCC, AUXVCC1 and AUXVCC2; connect the recommended capacitor CVSYS (Table 5-18).
11 P1.0/PM_TA0.0/VeREF-/A2 bidirectional General-purpose I/O with port interrupt and mappable function (default Timer TA0 CCR0 capture/compare); also negative ADC reference terminal for an external reference and 10-bit ADC analog input A2.
12 P1.1/PM_TA0.1/VeREF+/A1 bidirectional General-purpose I/O with port interrupt and mappable function (default Timer TA0 CCR1 capture/compare); also positive ADC reference terminal for an external reference and 10-bit ADC analog input A1.
13 P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0 bidirectional General-purpose I/O with port interrupt and mappable function (default eUSCI_A0 UART receive / SPI slave-out master-in); also 10-bit ADC analog input A0.
14 P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03 bidirectional General-purpose I/O with port interrupt and mappable function (default eUSCI_A0 UART transmit / SPI slave-in master-out); also LCD input/output port of the lowest analog LCD voltage (V5).
15 AUXVCC2 power_in Auxiliary power supply AUXVCC2.
16 AUXVCC1 power_in Auxiliary power supply AUXVCC1.
17 VDSYS power_in Digital power supply selected between DVCC, AUXVCC1 and AUXVCC2; must be connected externally on the board, with the recommended capacitor CVSYS (Table 5-18).
18 DVCC power_in Digital power supply.
19 DVSS power_in Digital ground supply.
20 VCORE power_in Regulated core power supply for internal use only; no external current loading is possible and it should only be connected to the recommended capacitor CVCORE.
21 XIN input Input terminal for the 32 kHz crystal oscillator.
22 XOUT output Output terminal for the 32 kHz crystal oscillator.
23 AUXVCC3 power_in Auxiliary power supply AUXVCC3 for the backup subsystem.
24 P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13 bidirectional General-purpose I/O with port interrupt and mappable function (default eUSCI_A1 UART receive / SPI slave-out master-in); also external reference input for the regulated LCD voltage and LCD port for V3/V4.
25 P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23 bidirectional General-purpose I/O with port interrupt and mappable function (default eUSCI_A1 UART transmit / SPI slave-in master-out); also LCD input/output port of the second most positive analog LCD voltage (V2).
26 LCDCAP/R33 bidirectional LCD capacitor connection and input/output port of the most positive analog LCD voltage (V1); must be connected to DVSS if not used.
27 COM0 output LCD common output COM0 for the LCD backplane.
28 COM1 output LCD common output COM1 for the LCD backplane.
29 COM2 output LCD common output COM2 for the LCD backplane.
30 COM3 output LCD common output COM3 for the LCD backplane.
31 P1.6/PM_UCA0CLK/COM4 bidirectional General-purpose I/O with port interrupt and mappable function (default eUSCI_A0 clock input/output); also LCD common output COM4.
32 P1.7/PM_UCB0CLK/COM5 bidirectional General-purpose I/O with port interrupt and mappable function (default eUSCI_B0 clock input/output); also LCD common output COM5.
33 P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6/S39 bidirectional General-purpose I/O with port interrupt and mappable function (default eUSCI_B0 SPI slave-out master-in / I2C clock); also LCD common output COM6 and LCD segment output S39.
34 P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7/S38 bidirectional General-purpose I/O with port interrupt and mappable function (default eUSCI_B0 SPI slave-in master-out / I2C data); also LCD common output COM7 and LCD segment output S38.
35 P2.2/PM_UCA2RXD/PM_UCA2SOMI/S37 bidirectional General-purpose I/O with port interrupt and mappable function (default eUSCI_A2 UART receive / SPI slave-out master-in); also LCD segment output S37.
36 P2.3/PM_UCA2TXD/PM_UCA2SIMO/S36 bidirectional General-purpose I/O with port interrupt and mappable function (default eUSCI_A2 UART transmit / SPI slave-in master-out); also LCD segment output S36.
37 P2.4/PM_UCA1CLK/S35 bidirectional General-purpose I/O with port interrupt and mappable function (default eUSCI_A1 clock input/output); also LCD segment output S35.
38 P2.5/PM_UCA2CLK/S34 bidirectional General-purpose I/O with port interrupt and mappable function (default eUSCI_A2 clock input/output); also LCD segment output S34.
39 P2.6/PM_TA1.0/S33 bidirectional General-purpose I/O with port interrupt and mappable function (default Timer TA1 CCR0 capture/compare); also LCD segment output S33.
40 P2.7/PM_TA1.1/S32 bidirectional General-purpose I/O with port interrupt and mappable function (default Timer TA1 CCR1 capture/compare); also LCD segment output S32.
41 P3.0/PM_TA2.0/S31/BSL_TX bidirectional General-purpose I/O with mappable function (default Timer TA2 CCR0 capture/compare); also LCD segment output S31 and bootloader data transmit.
42 P3.1/PM_TA2.1/S30/BSL_RX bidirectional General-purpose I/O with mappable function (default Timer TA2 CCR1 capture/compare); also LCD segment output S30 and bootloader data receive.
43 P3.2/PM_TACLK/PM_RTCCLK/S29 bidirectional General-purpose I/O with mappable function (default Timer clock input TACLK for TA0 to TA3, and RTCCLK clock output); also LCD segment output S29.
44 P3.3/PM_TA0.2/S28 bidirectional General-purpose I/O with mappable function (default Timer TA0 CCR2 capture/compare); also LCD segment output S28.
45 P3.4/PM_SDCLK/S27 bidirectional General-purpose I/O with mappable function (default SD24_B bitstream clock input/output); also LCD segment output S27.
46 P3.5/PM_SD0DIO/S26 bidirectional General-purpose I/O with mappable function (default SD24_B converter-0 bitstream data input/output); also LCD segment output S26.
47 P3.6/PM_SD1DIO/S25 bidirectional General-purpose I/O with mappable function (default SD24_B converter-1 bitstream data input/output); also LCD segment output S25.
48 P3.7/PM_NONE/S24 bidirectional General-purpose I/O with mappable function; on F672x devices there is no SD24_B converter-2 bitstream data function (PM_NONE), and it is also LCD segment output S24.
49 P4.0/S23 bidirectional General-purpose digital I/O; also LCD segment output S23.
50 P4.1/S22 bidirectional General-purpose digital I/O; also LCD segment output S22.
51 P4.2/S21 bidirectional General-purpose digital I/O; also LCD segment output S21.
52 P4.3/S20 bidirectional General-purpose digital I/O; also LCD segment output S20.
53 P4.4/S19 bidirectional General-purpose digital I/O; also LCD segment output S19.
54 P4.5/S18 bidirectional General-purpose digital I/O; also LCD segment output S18.
55 P4.6/S17 bidirectional General-purpose digital I/O; also LCD segment output S17.
56 P4.7/S16 bidirectional General-purpose digital I/O; also LCD segment output S16.
57 P5.0/S15 bidirectional General-purpose digital I/O; also LCD segment output S15.
58 P5.1/S14 bidirectional General-purpose digital I/O; also LCD segment output S14.
59 DVSYS power_in Digital power supply for I/Os; must be connected externally on the board for proper device operation.
60 DVSS power_in Digital ground supply.
61 P5.2/S13 bidirectional General-purpose digital I/O; also LCD segment output S13.
62 P5.3/S12 bidirectional General-purpose digital I/O; also LCD segment output S12.
63 P5.4/S11 bidirectional General-purpose digital I/O; also LCD segment output S11.
64 P5.5/S10 bidirectional General-purpose digital I/O; also LCD segment output S10.
65 P5.6/S9 bidirectional General-purpose digital I/O; also LCD segment output S9.
66 P5.7/S8 bidirectional General-purpose digital I/O; also LCD segment output S8.
67 P6.0/S7 bidirectional General-purpose digital I/O; also LCD segment output S7.
68 P6.1/S6 bidirectional General-purpose digital I/O; also LCD segment output S6.
69 P6.2/S5 bidirectional General-purpose digital I/O; also LCD segment output S5.
70 P6.3/S4 bidirectional General-purpose digital I/O; also LCD segment output S4.
71 P6.4/S3 bidirectional General-purpose digital I/O; also LCD segment output S3.
72 P6.5/S2 bidirectional General-purpose digital I/O; also LCD segment output S2.
73 P6.6/S1 bidirectional General-purpose digital I/O; also LCD segment output S1.
74 P6.7/S0 bidirectional General-purpose digital I/O; also LCD segment output S0.
75 TEST/SBWTCK input Test mode pin that selects digital I/O on the JTAG pins; also the Spy-Bi-Wire input clock.
76 PJ.0/SMCLK/TDO bidirectional General-purpose I/O; SMCLK clock output in normal mode and JTAG test data output (TDO).
77 PJ.1/MCLK/TDI/TCLK bidirectional General-purpose I/O; MCLK clock output in normal mode and JTAG test data input or test clock input (TDI/TCLK).
78 PJ.2/ADC10CLK/TMS bidirectional General-purpose I/O; ADC10_A clock output in normal mode and JTAG test mode select (TMS).
79 PJ.3/ACLK/TCK bidirectional General-purpose I/O; ACLK clock output in normal mode and JTAG test clock (TCK).
80 RST/NMI/SBWTDIO bidirectional Active-low reset input (internal pullup enabled by default when configured as reset), also nonmaskable interrupt input and Spy-Bi-Wire data input/output.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-80(12x12)
Category Embedded Processors & Controllers
Pins 80

CAD (KiCad official)

  • Symbol: MSP430F6723IPNR
  • Footprint: Package_QFP:LQFP-80_12x12mm_P0.5mm
  • 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: msp430f6723ipnr-etched.step / msp430f6723ipnr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430f6723ipnr.step / msp430f6723ipnr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (154 pp, sha256 3f8f4b9a2dc07004, retrieved 2026-10-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF