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MSP430F6723AIPNR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSP430F6723AIPNR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)

MSP430F6723AIPNR from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SD0P0 input SD24_B positive analog input for converter 0, with diode current limited to 2 mA and a protection diode to VCC only.
2 SD0N0 input SD24_B negative analog input for converter 0; TI recommends shorting unused analog input pairs to analog ground.
3 SD1P0 input SD24_B positive analog input for converter 1, with diode current limited to 2 mA and a protection diode to VCC only.
4 SD1N0 input SD24_B negative analog input for converter 1; TI recommends shorting unused analog input pairs to analog ground.
5 NC unconnected Not connected on MSP430F672xA devices, so the SD2P0 converter input is not available on this part.
6 NC unconnected Not connected on MSP430F672xA devices, so the SD2N0 converter input is not available on this part.
7 VREF power_in SD24_B external reference voltage input.
8 AVSS power_in Analog ground supply; V(AVSS) must equal V(DVSS) = VSS = 0 V.
9 AVCC power_in Analog power supply; TI recommends powering AVCC and DVCC from the same source with at most 0.3 V difference between them.
10 VASYS power_out Analog supply node selected among AVCC, AUXVCC1 and AUXVCC2; connect the recommended CVSYS capacitor (Table 5-18).
11 P1.0/PM_TA0.0/VeREF-/A2 bidirectional General-purpose digital I/O with port interrupt and mappable function (default PM_TA0.0, Timer_A TA0 CCR0); also ADC10 analog input A2 and negative reference VeREF-.
12 P1.1/PM_TA0.1/VeREF+/A1 bidirectional General-purpose digital I/O with port interrupt and mappable function (default PM_TA0.1, Timer_A TA0 CCR1); also ADC10 analog input A1 and positive reference VeREF+.
13 P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0 bidirectional General-purpose digital I/O with port interrupt and mappable function (default eUSCI_A0 UART RXD / SPI SOMI); also ADC10 analog input A0.
14 P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03 bidirectional General-purpose digital I/O with port interrupt and mappable function (default eUSCI_A0 UART TXD / SPI SIMO); also LCD voltage port R03 for the lowest analog LCD voltage V5.
15 AUXVCC2 power_in Auxiliary power supply AUXVCC2; can supply up to 20 mA to core and I/O and up to 5 mA to analog modules.
16 AUXVCC1 power_in Auxiliary power supply AUXVCC1; can supply up to 20 mA to core and I/O and up to 5 mA to analog modules.
17 VDSYS power_out Digital supply node selected between DVCC, AUXVCC1 and AUXVCC2; must be connected externally on board and connect the recommended CVSYS capacitor.
18 DVCC power_in Digital power supply; V(DVCC) = VCC is 1.8 V to 3.6 V for program execution and flash programming (PMMCOREVx dependent).
19 DVSS power_in Digital ground supply; V(DVSS) = VSS = 0 V, common with AVSS.
20 VCORE power_out Regulated core supply for internal use only; no external DC load or voltage may be applied, and only the recommended CVCORE = 470 nF capacitor should be connected.
21 XIN input Dedicated input terminal for the crystal oscillator; connect to DVSS if unused.
22 XOUT output Dedicated output terminal for the crystal oscillator; leave open if unused.
23 AUXVCC3 power_in Auxiliary power supply for the backup subsystem (XT1, RTC_C and backup RAM); absolute maximum voltage is VCC + 0.3 V.
24 P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13 bidirectional General-purpose digital I/O with port interrupt and mappable function (default eUSCI_A1 UART RXD / SPI SOMI); also LCD reference input LCDREF and LCD voltage port R13.
25 P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23 bidirectional General-purpose digital I/O with port interrupt and mappable function (default eUSCI_A1 UART TXD / SPI SIMO); also LCD voltage port R23 for the second most positive LCD voltage V2.
26 LCDCAP/R33 passive LCD capacitor connection, also LCD voltage port R33 for the most positive LCD voltage V1; must be connected to DVSS if not used.
27 COM0 output LCD common output COM0 for the LCD backplane.
28 COM1 output LCD common output COM1 for the LCD backplane.
29 COM2 output LCD common output COM2 for the LCD backplane.
30 COM3 output LCD common output COM3 for the LCD backplane.
31 P1.6/PM_UCA0CLK/COM4 bidirectional General-purpose digital I/O with port interrupt and mappable function (default eUSCI_A0 clock); shared with LCD common output COM4, which takes over the pin when enabled.
32 P1.7/PM_UCB0CLK/COM5 bidirectional General-purpose digital I/O with port interrupt and mappable function (default eUSCI_B0 clock); shared with LCD common output COM5, which takes over the pin when enabled.
33 P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6/S39 bidirectional General-purpose digital I/O with port interrupt and mappable function (default eUSCI_B0 SPI SOMI / I2C SCL); also LCD common COM6 and segment S39.
34 P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7/S38 bidirectional General-purpose digital I/O with port interrupt and mappable function (default eUSCI_B0 SPI SIMO / I2C SDA); also LCD common COM7 and segment S38.
35 P2.2/PM_UCA2RXD/PM_UCA2SOMI/S37 bidirectional General-purpose digital I/O with port interrupt and mappable function (default eUSCI_A2 UART RXD / SPI SOMI); also LCD segment output S37.
36 P2.3/PM_UCA2TXD/PM_UCA2SIMO/S36 bidirectional General-purpose digital I/O with port interrupt and mappable function (default eUSCI_A2 UART TXD / SPI SIMO); also LCD segment output S36.
37 P2.4/PM_UCA1CLK/S35 bidirectional General-purpose digital I/O with port interrupt and mappable function (default eUSCI_A1 clock); also LCD segment output S35.
38 P2.5/PM_UCA2CLK/S34 bidirectional General-purpose digital I/O with port interrupt and mappable function (default eUSCI_A2 clock); also LCD segment output S34.
39 P2.6/PM_TA1.0/S33 bidirectional General-purpose digital I/O with port interrupt and mappable function (default Timer_A TA1 CCR0); also LCD segment output S33.
40 P2.7/PM_TA1.1/S32 bidirectional General-purpose digital I/O with port interrupt and mappable function (default Timer_A TA1 CCR1); also LCD segment output S32.
41 P3.0/PM_TA2.0/S31 bidirectional General-purpose digital I/O with mappable function (default Timer_A TA2 CCR0, no port interrupt); also LCD segment output S31.
42 P3.1/PM_TA2.1/S30 bidirectional General-purpose digital I/O with mappable function (default Timer_A TA2 CCR1, no port interrupt); also LCD segment output S30 and bootloader BSL_RX input.
43 P3.2/PM_TACLK/PM_RTCCLK/S29 bidirectional General-purpose digital I/O with mappable function (default Timer_A TACLK input or RTC_C clock output); also LCD segment output S29.
44 P3.3/PM_TA0.2/S28 bidirectional General-purpose digital I/O with mappable function (default Timer_A TA0 CCR2); also LCD segment output S28.
45 P3.4/PM_SDCLK/S27 bidirectional General-purpose digital I/O with mappable function (default SD24_B bit-stream clock); also LCD segment output S27.
46 P3.5/PM_SD0DIO/S26 bidirectional General-purpose digital I/O with mappable function (default SD24_B converter 0 bit-stream data); also LCD segment output S26.
47 P3.6/PM_SD1DIO/S25 bidirectional General-purpose digital I/O with mappable function (default SD24_B converter 1 bit-stream data); also LCD segment output S25.
48 P3.7/PM_NONE/S24 bidirectional General-purpose digital I/O with mappable function; on F672xA devices the PM_SD2DIO function is not available and the mapping is PM_NONE, with LCD segment output S24.
49 P4.0/S23 bidirectional General-purpose digital I/O (no port interrupt); can be switched to LCD segment output S23.
50 P4.1/S22 bidirectional General-purpose digital I/O (no port interrupt); can be switched to LCD segment output S22.
51 P4.2/S21 bidirectional General-purpose digital I/O (no port interrupt); can be switched to LCD segment output S21.
52 P4.3/S20 bidirectional General-purpose digital I/O (no port interrupt); can be switched to LCD segment output S20.
53 P4.4/S19 bidirectional General-purpose digital I/O (no port interrupt); can be switched to LCD segment output S19.
54 P4.5/S18 bidirectional General-purpose digital I/O (no port interrupt); can be switched to LCD segment output S18.
55 P4.6/S17 bidirectional General-purpose digital I/O (no port interrupt); can be switched to LCD segment output S17.
56 P4.7/S16 bidirectional General-purpose digital I/O (no port interrupt); can be switched to LCD segment output S16.
57 P5.0/S15 bidirectional General-purpose digital I/O (no port interrupt); can be switched to LCD segment output S15.
58 P5.1/S14 bidirectional General-purpose digital I/O (no port interrupt); can be switched to LCD segment output S14.
59 DVSYS power_in Digital power supply for I/Os; must be connected externally on board for proper device operation.
60 DVSS power_in Digital ground supply, common with DVSS pin 19.
61 P5.2/S13 bidirectional General-purpose digital I/O (no port interrupt); can be switched to LCD segment output S13.
62 P5.3/S12 bidirectional General-purpose digital I/O (no port interrupt); can be switched to LCD segment output S12.
63 P5.4/S11 bidirectional General-purpose digital I/O (no port interrupt); can be switched to LCD segment output S11.
64 P5.5/S10 bidirectional General-purpose digital I/O (no port interrupt); can be switched to LCD segment output S10.
65 P5.6/S9 bidirectional General-purpose digital I/O (no port interrupt); can be switched to LCD segment output S9.
66 P5.7/S8 bidirectional General-purpose digital I/O (no port interrupt); can be switched to LCD segment output S8.
67 P6.0/S7 bidirectional General-purpose digital I/O (no port interrupt); can be switched to LCD segment output S7.
68 P6.1/S6 bidirectional General-purpose digital I/O (no port interrupt); can be switched to LCD segment output S6.
69 P6.2/S5 bidirectional General-purpose digital I/O (no port interrupt); can be switched to LCD segment output S5.
70 P6.3/S4 bidirectional General-purpose digital I/O (no port interrupt); can be switched to LCD segment output S4.
71 P6.4/S3 bidirectional General-purpose digital I/O (no port interrupt); can be switched to LCD segment output S3.
72 P6.5/S2 bidirectional General-purpose digital I/O (no port interrupt); can be switched to LCD segment output S2.
73 P6.6/S1 bidirectional General-purpose digital I/O (no port interrupt); can be switched to LCD segment output S1.
74 P6.7/S0 bidirectional General-purpose digital I/O (no port interrupt); can be switched to LCD segment output S0.
75 TEST/SBWTCK input Test mode pin that selects digital I/O on the JTAG pins and always has an internal pulldown enabled; also Spy-Bi-Wire clock input SBWTCK.
76 PJ.0/SMCLK/TDO bidirectional Port PJ.0 general-purpose I/O (no interrupt); SMCLK clock output in port mode and JTAG TDO output in JTAG mode.
77 PJ.1/MCLK/TDI/TCLK bidirectional Port PJ.1 general-purpose I/O (no interrupt); MCLK clock output in port mode and JTAG TDI/TCLK input in JTAG mode.
78 PJ.2/ADC10CLK/TMS bidirectional Port PJ.2 general-purpose I/O (no interrupt); ADC10CLK output in port mode and JTAG TMS input in JTAG mode, with pullup active in JTAG mode.
79 PJ.3/ACLK/TCK bidirectional Port PJ.3 general-purpose I/O (no interrupt); ACLK clock output in port mode and JTAG TCK input in JTAG mode, with pullup active in JTAG mode.
80 RST/NMI/SBWTDIO bidirectional Active-low reset input with internal pullup enabled by default when configured as reset; also NMI input and Spy-Bi-Wire data I/O.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-80(12x12)
Category Embedded Processors & Controllers
Pins 80

CAD (KiCad official)

  • Symbol: MSP430F6723AIPNR
  • Footprint: Package_QFP:LQFP-80_12x12mm_P0.5mm
  • 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: msp430f6723aipnr-etched.step / msp430f6723aipnr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430f6723aipnr.step / msp430f6723aipnr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (168 pp, sha256 9f50329e4202500f, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF