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MSP430F5529IPNR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430F5529IPNR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)
MSP430F5529IPNR from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P6.4/CB4/A4 | bidirectional | Configurable as general-purpose digital I/O, Comparator_B input CB4, or analog input A4 for ADC. |
| 2 | P6.5/CB5/A5 | bidirectional | Configurable as general-purpose digital I/O, Comparator_B input CB5, or analog input A5 for ADC. |
| 3 | P6.6/CB6/A6 | bidirectional | Configurable as general-purpose digital I/O, Comparator_B input CB6, or analog input A6 for ADC. |
| 4 | P6.7/CB7/A7 | bidirectional | Configurable as general-purpose digital I/O, Comparator_B input CB7, or analog input A7 for ADC. |
| 5 | P7.0/CB8/A12 | bidirectional | Configurable as general-purpose digital I/O, Comparator_B input CB8, or analog input A12 for ADC. |
| 6 | P7.1/CB9/A13 | bidirectional | Configurable as general-purpose digital I/O, Comparator_B input CB9, or analog input A13 for ADC. |
| 7 | P7.2/CB10/A14 | bidirectional | Configurable as general-purpose digital I/O, Comparator_B input CB10, or analog input A14 for ADC. |
| 8 | P7.3/CB11/A15 | bidirectional | Configurable as general-purpose digital I/O, Comparator_B input CB11, or analog input A15 for ADC. |
| 9 | P5.0/A8/VREF+/VeREF+ | bidirectional | General-purpose digital I/O, analog input A8 for ADC, output or input for external ADC reference voltage. |
| 10 | P5.1/A9/VREF−/VeREF− | bidirectional | General-purpose digital I/O, analog input A9 for ADC, negative terminal for ADC reference voltage from internal or external source. |
| 11 | AVCC1 | power_in | Analog power supply. |
| 12 | P5.4/XIN | bidirectional | Configurable as general-purpose digital I/O or input terminal for crystal oscillator XT1. |
| 13 | P5.5/XOUT | bidirectional | Configurable as general-purpose digital I/O or output terminal of crystal oscillator XT1. |
| 14 | AVSS1 | power_in | Analog ground supply. |
| 15 | P8.0 | bidirectional | General-purpose digital I/O. |
| 16 | P8.1 | bidirectional | General-purpose digital I/O. |
| 17 | P8.2 | bidirectional | General-purpose digital I/O. |
| 18 | DVCC1 | power_in | Digital power supply. |
| 19 | DVSS1 | power_in | Digital ground supply. |
| 20 | VCORE | power_out | Regulated core power supply output for internal use only; connect to recommended capacitor value. |
| 21 | P1.0/TA0CLK/ACLK | bidirectional | General-purpose digital I/O with port interrupt, TA0 clock signal input, or ACLK output divided by 1, 2, 4, 8, 16, or 32. |
| 22 | P1.1/TA0.0 | bidirectional | General-purpose digital I/O with port interrupt, TA0 capture input CCI0A or compare output Out0, or BSL transmit output. |
| 23 | P1.2/TA0.1 | bidirectional | General-purpose digital I/O with port interrupt, TA0 capture input CCI1A or compare output Out1, or BSL receive input. |
| 24 | P1.3/TA0.2 | bidirectional | General-purpose digital I/O with port interrupt, TA0 capture input CCI2A or compare output Out2. |
| 25 | P1.4/TA0.3 | bidirectional | General-purpose digital I/O with port interrupt, TA0 capture input CCI3A or compare output Out3. |
| 26 | P1.5/TA0.4 | bidirectional | General-purpose digital I/O with port interrupt, TA0 capture input CCI4A or compare output Out4. |
| 27 | P1.6/TA1CLK/CBOUT | bidirectional | General-purpose digital I/O with port interrupt, TA1 clock signal input, or Comparator_B output. |
| 28 | P1.7/TA1.0 | bidirectional | General-purpose digital I/O with port interrupt, TA1 capture input CCI0A or compare output Out0. |
| 29 | P2.0/TA1.1 | bidirectional | General-purpose digital I/O with port interrupt, TA1 capture input CCI1A or compare output Out1. |
| 30 | P2.1/TA1.2 | bidirectional | General-purpose digital I/O with port interrupt, TA1 capture input CCI2A or compare output Out2. |
| 31 | P2.2/TA2CLK/SMCLK | bidirectional | General-purpose digital I/O with port interrupt, TA2 clock signal input, or SMCLK output. |
| 32 | P2.3/TA2.0 | bidirectional | General-purpose digital I/O with port interrupt, TA2 capture input CCI0A or compare output Out0. |
| 33 | P2.4/TA2.1 | bidirectional | General-purpose digital I/O with port interrupt, TA2 capture input CCI1A or compare output Out1. |
| 34 | P2.5/TA2.2 | bidirectional | General-purpose digital I/O with port interrupt, TA2 capture input CCI2A or compare output Out2. |
| 35 | P2.6/RTCCLK/DMAE0 | bidirectional | General-purpose digital I/O with port interrupt, RTC clock output for calibration, or DMA external trigger input. |
| 36 | P2.7/UCB0STE/UCA0CLK | bidirectional | General-purpose digital I/O with port interrupt, USCI_B0 SPI slave transmit enable, or USCI_A0 SPI clock signal. |
| 37 | P3.0/UCB0SIMO/UCB0SDA | bidirectional | General-purpose digital I/O, USCI_B0 SPI slave in master out, or USCI_B0 I2C data. |
| 38 | P3.1/UCB0SOMI/UCB0SCL | bidirectional | General-purpose digital I/O, USCI_B0 SPI slave out master in, or USCI_B0 I2C clock. |
| 39 | P3.2/UCB0CLK/UCA0STE | bidirectional | General-purpose digital I/O, USCI_B0 SPI clock signal, or USCI_A0 SPI slave transmit enable. |
| 40 | P3.3/UCA0TXD/UCA0SIMO | bidirectional | General-purpose digital I/O, USCI_A0 UART transmit data, or USCI_A0 SPI slave in master out. |
| 41 | P3.4/UCA0RXD/UCA0SOMI | bidirectional | General-purpose digital I/O, USCI_A0 UART receive data, or USCI_A0 SPI slave out master in. |
| 42 | P3.5/TB0.5 | bidirectional | General-purpose digital I/O, TB0 capture input CCI5A or compare output Out5. |
| 43 | P3.6/TB0.6 | bidirectional | General-purpose digital I/O, TB0 capture input CCI6A or compare output Out6. |
| 44 | P3.7/TB0OUTH/SVMOUT | bidirectional | General-purpose digital I/O, TB0 high impedance input, or SVM output. |
| 45 | P4.0/PM_UCB1STE/PM_UCA1CLK | bidirectional | General-purpose digital I/O with reconfigurable port mapping, default USCI_B1 SPI slave transmit enable or USCI_A1 SPI clock. |
| 46 | P4.1/PM_UCB1SIMO/PM_UCB1SDA | bidirectional | General-purpose digital I/O with reconfigurable port mapping, default USCI_B1 SPI slave in master out or USCI_B1 I2C data. |
| 47 | P4.2/PM_UCB1SOMI/PM_UCB1SCL | bidirectional | General-purpose digital I/O with reconfigurable port mapping, default USCI_B1 SPI slave out master in or USCI_B1 I2C clock. |
| 48 | P4.3/PM_UCB1CLK/PM_UCA1STE | bidirectional | General-purpose digital I/O with reconfigurable port mapping, default USCI_B1 SPI clock or USCI_A1 SPI slave transmit enable. |
| 49 | DVSS2 | power_in | Digital ground supply. |
| 50 | DVCC2 | power_in | Digital power supply. |
| 51 | P4.4/PM_UCA1TXD/PM_UCA1SIMO | bidirectional | General-purpose digital I/O with reconfigurable port mapping, default USCI_A1 UART transmit data or USCI_A1 SPI slave in master out. |
| 52 | P4.5/PM_UCA1RXD/PM_UCA1SOMI | bidirectional | General-purpose digital I/O with reconfigurable port mapping, default USCI_A1 UART receive data or USCI_A1 SPI slave out master in. |
| 53 | P4.6/PM_NONE | bidirectional | General-purpose digital I/O with reconfigurable port mapping and no default secondary function. |
| 54 | P4.7/PM_NONE | bidirectional | General-purpose digital I/O with reconfigurable port mapping and no default secondary function. |
| 55 | P5.6/TB0.0 | bidirectional | General-purpose digital I/O, TB0 capture input CCI0A or compare output Out0. |
| 56 | P5.7/TB0.1 | bidirectional | General-purpose digital I/O, TB0 capture input CCI1A or compare output Out1. |
| 57 | P7.4/TB0.2 | bidirectional | General-purpose digital I/O, TB0 capture input CCI2A or compare output Out2. |
| 58 | P7.5/TB0.3 | bidirectional | General-purpose digital I/O, TB0 capture input CCI3A or compare output Out3. |
| 59 | P7.6/TB0.4 | bidirectional | General-purpose digital I/O, TB0 capture input CCI4A or compare output Out4. |
| 60 | P7.7/TB0CLK/MCLK | bidirectional | General-purpose digital I/O, TB0 clock signal input, or MCLK output. |
| 61 | VSSU | power_in | USB PHY ground supply. |
| 62 | PU.0/DP | bidirectional | General-purpose digital I/O controlled by USB control register or USB data terminal DP. |
| 63 | PUR | bidirectional | USB pullup resistor pin with open drain output; voltage level invokes default USB bootloader loader mode with recommended 1-MΩ resistor to ground. |
| 64 | PU.1/DM | bidirectional | General-purpose digital I/O controlled by USB control register or USB data terminal DM. |
| 65 | VBUS | power_in | USB LDO input connected to USB power source. |
| 66 | VUSB | power_out | USB LDO output providing regulated 3.3 V USB power supply. |
| 67 | V18 | power_out | USB regulated 1.8 V power for internal use only; no external current loading is possible. |
| 68 | AVSS2 | power_in | Analog ground supply. |
| 69 | P5.2/XT2IN | bidirectional | Configurable as general-purpose digital I/O or input terminal for crystal oscillator XT2. |
| 70 | P5.3/XT2OUT | bidirectional | Configurable as general-purpose digital I/O or output terminal of crystal oscillator XT2. |
| 71 | TEST/SBWTCK | input | Test mode pin for 4-wire JTAG operation or Spy-Bi-Wire input clock when activated. |
| 72 | PJ.0/TDO | bidirectional | General-purpose digital I/O or JTAG test data output port. |
| 73 | PJ.1/TDI/TCLK | bidirectional | General-purpose digital I/O, JTAG test data input, or test clock input. |
| 74 | PJ.2/TMS | bidirectional | General-purpose digital I/O or JTAG test mode select. |
| 75 | PJ.3/TCK | bidirectional | General-purpose digital I/O or JTAG test clock. |
| 76 | RST/NMI/SBWTDIO | bidirectional | Reset input active low with internal pullup resistor, nonmaskable interrupt input, or Spy-Bi-Wire data input/output when activated. |
| 77 | P6.0/CB0/A0 | bidirectional | Configurable as general-purpose digital I/O, Comparator_B input CB0, or analog input A0 for ADC. |
| 78 | P6.1/CB1/A1 | bidirectional | Configurable as general-purpose digital I/O, Comparator_B input CB1, or analog input A1 for ADC. |
| 79 | P6.2/CB2/A2 | bidirectional | Configurable as general-purpose digital I/O, Comparator_B input CB2, or analog input A2 for ADC. |
| 80 | P6.3/CB3/A3 | bidirectional | Configurable as general-purpose digital I/O, Comparator_B input CB3, or analog input A3 for ADC. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-80(12x12) |
| Category | Embedded Processors & Controllers |
| Pins | 80 |
CAD (KiCad official)
- Symbol:
MSP430F5529IPNR - Footprint:
Package_QFP:LQFP-80_12x12mm_P0.5mm - 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
- 3D model files:
msp430f5529ipnr-etched.step/msp430f5529ipnr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430f5529ipnr.step/msp430f5529ipnr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (143 pp, sha256
6524c2111d233bdc, retrieved 2026-09-30, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).