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MSP430F5529IPN

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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MSP430F5529IPN

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)

MSP430F5529IPN from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P6.4/CB4/A4 bidirectional General-purpose digital I/O with Comparator_B input CB4 and ADC analog input A4 functions (not available on F551x devices).
2 P6.5/CB5/A5 bidirectional General-purpose digital I/O with Comparator_B input CB5 and ADC analog input A5 functions (not available on F551x devices).
3 P6.6/CB6/A6 bidirectional General-purpose digital I/O with Comparator_B input CB6 and ADC analog input A6 functions (not available on F551x devices).
4 P6.7/CB7/A7 bidirectional General-purpose digital I/O with Comparator_B input CB7 and ADC analog input A7 functions (not available on F551x devices).
5 P7.0/CB8/A12 bidirectional General-purpose digital I/O with Comparator_B input CB8 and ADC analog input A12 functions (not available on F5528, F5526, F5524, F5522, F5514, F5513 and F551x devices).
6 P7.1/CB9/A13 bidirectional General-purpose digital I/O with Comparator_B input CB9 and ADC analog input A13 functions (not available on F5528, F5526, F5524, F5522, F5514, F5513 and F551x devices).
7 P7.2/CB10/A14 bidirectional General-purpose digital I/O with Comparator_B input CB10 and ADC analog input A14 functions (not available on F5528, F5526, F5524, F5522, F5514, F5513 and F551x devices).
8 P7.3/CB11/A15 bidirectional General-purpose digital I/O with Comparator_B input CB11 and ADC analog input A15 functions (not available on F5528, F5526, F5524, F5522, F5514, F5513 and F551x devices).
9 P5.0/A8/VREF+/VeREF+ bidirectional General-purpose digital I/O or ADC analog input A8 with configurable output of internal reference voltage or input for external reference voltage to ADC (not available on F551x devices).
10 P5.1/A9/VREF-/VeREF- bidirectional General-purpose digital I/O or ADC analog input A9 with negative terminal for ADC reference voltage (internal or external source, not available on F551x devices).
11 AVCC1 power_in Analog power supply input for ADC and reference voltage circuits with recommended decoupling capacitor 1 µF.
12 P5.4/XIN bidirectional General-purpose digital I/O or input terminal for XT1 low-frequency crystal oscillator in 32 kHz mode.
13 P5.5/XOUT bidirectional General-purpose digital I/O or output terminal for XT1 low-frequency crystal oscillator in 32 kHz mode.
14 AVSS1 power_in Analog ground supply reference for ADC and analog circuits.
15 P8.0 bidirectional General-purpose digital I/O port available only on 80-pin PN packages.
16 P8.1 bidirectional General-purpose digital I/O port available only on 80-pin PN packages.
17 P8.2 bidirectional General-purpose digital I/O port available only on 80-pin PN packages.
18 DVCC1 power_in Digital power supply input (1.8V to 3.6V) with recommended decoupling capacitor 1 µF to VSS.
19 DVSS1 power_in Digital ground supply return path.
20 VCORE power_out Regulated core power supply output for internal use only with recommended 470 nF bypass capacitor, no external current loading permitted.
21 P1.0/TA0CLK/ACLK bidirectional General-purpose digital I/O with port interrupt or TA0 clock input or ACLK output (divided by 1/2/4/8/16/32).
22 P1.1/TA0.0 bidirectional General-purpose digital I/O with port interrupt or TA0 CCR0 capture input CCI0A or compare output or BSL transmit.
23 P1.2/TA0.1 bidirectional General-purpose digital I/O with port interrupt or TA0 CCR1 capture input CCI1A or compare output or BSL receive.
24 P1.3/TA0.2 bidirectional General-purpose digital I/O with port interrupt or TA0 CCR2 capture input CCI2A or compare output.
25 P1.4/TA0.3 bidirectional General-purpose digital I/O with port interrupt or TA0 CCR3 capture input CCI3A or compare output.
26 P1.5/TA0.4 bidirectional General-purpose digital I/O with port interrupt or TA0 CCR4 capture input CCI4A or compare output.
27 P1.6/TA1CLK/CBOUT bidirectional General-purpose digital I/O with port interrupt or TA1 clock input or Comparator_B output.
28 P1.7/TA1.0 bidirectional General-purpose digital I/O with port interrupt or TA1 CCR0 capture input CCI0A or compare output.
29 P2.0/TA1.1 bidirectional General-purpose digital I/O with port interrupt or TA1 CCR1 capture input CCI1A or compare output.
30 P2.1/TA1.2 bidirectional General-purpose digital I/O with port interrupt or TA1 CCR2 capture input CCI2A or compare output.
31 P2.2/TA2CLK/SMCLK bidirectional General-purpose digital I/O with port interrupt or TA2 clock input or SMCLK output.
32 P2.3/TA2.0 bidirectional General-purpose digital I/O with port interrupt or TA2 CCR0 capture input CCI0A or compare output.
33 P2.4/TA2.1 bidirectional General-purpose digital I/O with port interrupt or TA2 CCR1 capture input CCI1A or compare output.
34 P2.5/TA2.2 bidirectional General-purpose digital I/O with port interrupt or TA2 CCR2 capture input CCI2A or compare output.
35 P2.6/RTCCLK/DMAE0 bidirectional General-purpose digital I/O with port interrupt or RTC clock output for calibration or DMA external trigger input.
36 P2.7/UCB0STE/UCA0CLK bidirectional General-purpose digital I/O with port interrupt or USCI_B0 SPI slave transmit enable or USCI_A0 SPI clock input/output.
37 P3.0/UCB0SIMO/UCB0SDA bidirectional General-purpose digital I/O or USCI_B0 SPI slave in master out or I2C data SDA line.
38 P3.1/UCB0SOMI/UCB0SCL bidirectional General-purpose digital I/O or USCI_B0 SPI slave out master in or I2C clock SCL line.
39 P3.2/UCB0CLK/UCA0STE bidirectional General-purpose digital I/O or USCI_B0 SPI clock input/output or USCI_A0 SPI slave transmit enable.
40 P3.3/UCA0TXD/UCA0SIMO bidirectional General-purpose digital I/O or USCI_A0 UART transmit data or SPI slave in master out.
41 P3.4/UCA0RXD/UCA0SOMI bidirectional General-purpose digital I/O or USCI_A0 UART receive data or SPI slave out master in.
42 P3.5/TB0.5 bidirectional General-purpose digital I/O or TB0 CCR5 capture input CCI5A or compare output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices).
43 P3.6/TB0.6 bidirectional General-purpose digital I/O or TB0 CCR6 capture input CCI6A or compare output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices).
44 P3.7/TB0OUTH/SVMOUT bidirectional General-purpose digital I/O or TB0 switch all PWM outputs high impedance input or SVM output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices).
45 P4.0/PM_UCB1STE/PM_UCA1CLK bidirectional General-purpose digital I/O with reconfigurable port mapping or USCI_B1 SPI slave transmit enable or USCI_A1 SPI clock input/output.
46 P4.1/PM_UCB1SIMO/PM_UCB1SDA bidirectional General-purpose digital I/O with reconfigurable port mapping or USCI_B1 SPI slave in master out or I2C data SDA line.
47 P4.2/PM_UCB1SOMI/PM_UCB1SCL bidirectional General-purpose digital I/O with reconfigurable port mapping or USCI_B1 SPI slave out master in or I2C clock SCL line.
48 P4.3/PM_UCB1CLK/PM_UCA1STE bidirectional General-purpose digital I/O with reconfigurable port mapping or USCI_B1 SPI clock input/output or USCI_A1 SPI slave transmit enable.
49 DVSS2 power_in Digital ground supply return path.
50 DVCC2 power_in Digital power supply input (1.8V to 3.6V) with recommended decoupling capacitor 1 µF to VSS.
51 P4.4/PM_UCA1TXD/PM_UCA1SIMO bidirectional General-purpose digital I/O with reconfigurable port mapping or USCI_A1 UART transmit data or SPI slave in master out.
52 P4.5/PM_UCA1RXD/PM_UCA1SOMI bidirectional General-purpose digital I/O with reconfigurable port mapping or USCI_A1 UART receive data or SPI slave out master in.
53 P4.6/PM_NONE bidirectional General-purpose digital I/O with reconfigurable port mapping and default no secondary function.
54 P4.7/PM_NONE bidirectional General-purpose digital I/O with reconfigurable port mapping and default no secondary function.
55 P5.6/TB0.0 bidirectional General-purpose digital I/O or TB0 CCR0 capture input CCI0A or compare output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices).
56 P5.7/TB0.1 bidirectional General-purpose digital I/O or TB0 CCR1 capture input CCI1A or compare output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices).
57 P7.4/TB0.2 bidirectional General-purpose digital I/O or TB0 CCR2 capture input CCI2A or compare output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices).
58 P7.5/TB0.3 bidirectional General-purpose digital I/O or TB0 CCR3 capture input CCI3A or compare output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices).
59 P7.6/TB0.4 bidirectional General-purpose digital I/O or TB0 CCR4 capture input CCI4A or compare output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices).
60 P7.7/TB0CLK/MCLK bidirectional General-purpose digital I/O or TB0 clock input TBCLK or MCLK output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices).
61 VSSU power_in USB PHY ground supply reference.
62 PU.0/DP bidirectional General-purpose digital I/O controlled by USB control register or USB data terminal DP line.
63 PUR bidirectional USB pullup resistor pin with open-drain output for voltage level detection to invoke default USB BSL (recommended 1 MΩ resistor to ground).
64 PU.1/DM bidirectional General-purpose digital I/O controlled by USB control register or USB data terminal DM line.
65 VBUS power_in USB LDO input (connect to USB 5V power source or 3.3V supply).
66 VUSB power_out USB LDO output providing 3.3V power for USB PHY and digital I/O (connect 1 µF decoupling capacitor).
67 V18 power_out USB regulated 1.8V power for internal use only with no external current loading permitted.
68 AVSS2 power_in Analog ground supply reference for USB PHY circuits.
69 P5.2/XT2IN bidirectional General-purpose digital I/O or input terminal for XT2 high-frequency crystal oscillator (up to 32 MHz).
70 P5.3/XT2OUT bidirectional General-purpose digital I/O or output terminal for XT2 high-frequency crystal oscillator (up to 32 MHz).
71 TEST/SBWTCK input Test mode input pin selecting 4-wire JTAG operation or Spy-Bi-Wire input clock when SBW protocol activated.
72 PJ.0/TDO bidirectional General-purpose digital I/O or JTAG test data output port TDO.
73 PJ.1/TDI/TCLK bidirectional General-purpose digital I/O or JTAG test data input TDI or test clock input TCLK.
74 PJ.2/TMS bidirectional General-purpose digital I/O or JTAG test mode select input TMS.
75 PJ.3/TCK bidirectional General-purpose digital I/O or JTAG test clock input TCK.
76 RST/NMI/SBWTDIO bidirectional Reset input active low with internal pull-up resistor or nonmaskable interrupt input or Spy-Bi-Wire data I/O when SBW protocol activated.
77 P6.0/CB0/A0 bidirectional General-purpose digital I/O with Comparator_B input CB0 and ADC analog input A0 functions (not available on F551x devices).
78 P6.1/CB1/A1 bidirectional General-purpose digital I/O with Comparator_B input CB1 and ADC analog input A1 functions (not available on F551x devices).
79 P6.2/CB2/A2 bidirectional General-purpose digital I/O with Comparator_B input CB2 and ADC analog input A2 functions (not available on F551x devices).
80 P6.3/CB3/A3 bidirectional General-purpose digital I/O with Comparator_B input CB3 and ADC analog input A3 functions (not available on F551x devices).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-80(12x12)
Category Embedded Processors & Controllers
Pins 80

CAD (KiCad official)

  • Symbol: MSP430F5529IPN
  • Footprint: Package_QFP:LQFP-80_12x12mm_P0.5mm
  • 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: msp430f5529ipn-etched.step / msp430f5529ipn-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430f5529ipn.step / msp430f5529ipn.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (143 pp, sha256 6524c2111d233bdc, retrieved 2026-10-05, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF