component
MSP430F5526IRGCR
Public Made by Adomby adom
Texas Instruments Microcontroller Units (MCUs/MPUs/SOCs), VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430F5526IRGCR
Texas Instruments · Microcontroller Units (MCUs/MPUs/SOCs) · VQFN-64-EP(9x9)
MSP430F5526IRGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P6.0/CB0/A0 | bidirectional | General-purpose digital I/O with Comparator_B input CB0 and ADC analog input A0 (A0 not available on F551x devices). |
| 2 | P6.1/CB1/A1 | bidirectional | General-purpose digital I/O with Comparator_B input CB1 and ADC analog input A1 (A1 not available on F551x devices). |
| 3 | P6.2/CB2/A2 | bidirectional | General-purpose digital I/O with Comparator_B input CB2 and ADC analog input A2 (A2 not available on F551x devices). |
| 4 | P6.3/CB3/A3 | bidirectional | General-purpose digital I/O with Comparator_B input CB3 and ADC analog input A3 (A3 not available on F551x devices). |
| 5 | P6.4/CB4/A4 | bidirectional | General-purpose digital I/O with Comparator_B input CB4 and ADC analog input A4 (A4 not available on F551x devices). |
| 6 | P6.5/CB5/A5 | bidirectional | General-purpose digital I/O with Comparator_B input CB5 and ADC analog input A5 (A5 not available on F551x devices). |
| 7 | P6.6/CB6/A6 | bidirectional | General-purpose digital I/O with Comparator_B input CB6 and ADC analog input A6 (A6 not available on F551x devices). |
| 8 | P6.7/CB7/A7 | bidirectional | General-purpose digital I/O with Comparator_B input CB7 and ADC analog input A7 (A7 not available on F551x devices). |
| 9 | P5.0/A8/VREF+/VeREF+ | bidirectional | General-purpose digital I/O that can also output the ADC reference voltage, accept an external ADC reference input, or serve as ADC analog input A8 (not available on F551x devices). |
| 10 | P5.1/A9/VREF-/VeREF- | bidirectional | General-purpose digital I/O that serves as the negative ADC reference terminal or ADC analog input A9 (not available on F551x devices). |
| 11 | AVCC1 | power_in | Analog power supply; TI recommends powering AVCC and DVCC from the same source with at most 0.3 V difference. |
| 12 | P5.4/XIN | bidirectional | General-purpose digital I/O that becomes the input terminal for crystal oscillator XT1 when crystal mode is selected. |
| 13 | P5.5/XOUT | bidirectional | General-purpose digital I/O that becomes the output terminal of crystal oscillator XT1 when crystal mode is selected. |
| 14 | AVSS1 | power_in | Analog ground supply. |
| 15 | DVCC1 | power_in | Digital power supply. |
| 16 | DVSS1 | power_in | Digital ground supply. |
| 17 | VCORE | power_out | Regulated core power supply output for internal use only; no external current loading is possible and the recommended capacitor is 470 nF. |
| 18 | P1.0/TA0CLK/ACLK | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are the TA0 clock input TA0CLK and the ACLK output divided by 1, 2, 4, 8, 16, or 32. |
| 19 | P1.1/TA0.0 | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are TA0 CCR0 capture input CCI0A or compare output Out0, and the BSL transmit output. |
| 20 | P1.2/TA0.1 | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are TA0 CCR1 capture input CCI1A or compare output Out1, and the BSL receive input. |
| 21 | P1.3/TA0.2 | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are TA0 CCR2 capture input CCI2A or compare output Out2. |
| 22 | P1.4/TA0.3 | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are TA0 CCR3 capture input CCI3A or compare output Out3. |
| 23 | P1.5/TA0.4 | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are TA0 CCR4 capture input CCI4A or compare output Out4. |
| 24 | P1.6/TA1CLK/CBOUT | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are the TA1 clock input TA1CLK and the Comparator_B output CBOUT. |
| 25 | P1.7/TA1.0 | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are TA1 CCR0 capture input CCI0A or compare output Out0. |
| 26 | P2.0/TA1.1 | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are TA1 CCR1 capture input CCI1A or compare output Out1. |
| 27 | P2.1/TA1.2 | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are TA1 CCR2 capture input CCI2A or compare output Out2. |
| 28 | P2.2/TA2CLK/SMCLK | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are the TA2 clock input TA2CLK and the SMCLK output. |
| 29 | P2.3/TA2.0 | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are TA2 CCR0 capture input CCI0A or compare output Out0. |
| 30 | P2.4/TA2.1 | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are TA2 CCR1 capture input CCI1A or compare output Out1. |
| 31 | P2.5/TA2.2 | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are TA2 CCR2 capture input CCI2A or compare output Out2. |
| 32 | P2.6/RTCCLK/DMAE0 | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are the RTC clock output for calibration and the DMA external trigger input DMAE0. |
| 33 | P2.7/UCB0STE/UCA0CLK | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are the USCI_B0 SPI slave transmit enable, and the USCI_A0 SPI clock signal input (slave) or output (master). |
| 34 | P3.0/UCB0SIMO/UCB0SDA | bidirectional | General-purpose digital I/O; alternate functions are USCI_B0 SPI slave-in/master-out and the USCI_B0 I2C data line. |
| 35 | P3.1/UCB0SOMI/UCB0SCL | bidirectional | General-purpose digital I/O; alternate functions are USCI_B0 SPI slave-out/master-in and the USCI_B0 I2C clock line. |
| 36 | P3.2/UCB0CLK/UCA0STE | bidirectional | General-purpose digital I/O; alternate functions are the USCI_B0 SPI clock input or output and the USCI_A0 SPI slave transmit enable. |
| 37 | P3.3/UCA0TXD/UCA0SIMO | bidirectional | General-purpose digital I/O; alternate functions are USCI_A0 UART transmit data and USCI_A0 SPI slave-in/master-out. |
| 38 | P3.4/UCA0RXD/UCA0SOMI | bidirectional | General-purpose digital I/O; alternate functions are USCI_A0 UART receive data and USCI_A0 SPI slave-out/master-in. |
| 39 | DVSS2 | power_in | Digital ground supply. |
| 40 | DVCC2 | power_in | Digital power supply. |
| 41 | P4.0/PM_UCB1STE/PM_UCA1CLK | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI slave transmit enable and USCI_A1 clock input/output. |
| 42 | P4.1/PM_UCB1SIMO/PM_UCB1SDA | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI slave-in/master-out and USCI_B1 I2C data. |
| 43 | P4.2/PM_UCB1SOMI/PM_UCB1SCL | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI slave-out/master-in and USCI_B1 I2C clock. |
| 44 | P4.3/PM_UCB1CLK/PM_UCA1STE | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI clock input/output and USCI_A1 SPI slave transmit enable. |
| 45 | P4.4/PM_UCA1TXD/PM_UCA1SIMO | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_A1 UART transmit data and USCI_A1 SPI slave-in/master-out. |
| 46 | P4.5/PM_UCA1RXD/PM_UCA1SOMI | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_A1 UART receive data and USCI_A1 SPI slave-out/master-in. |
| 47 | P4.6/PM_NONE | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping has no secondary function. |
| 48 | P4.7/PM_NONE | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping has no secondary function. |
| 49 | VSSU | power_in | USB PHY ground supply. |
| 50 | PU.0/DP | bidirectional | General-purpose digital I/O controlled by the USB control register, or the USB data terminal DP; PU.1/DM and PU.0/DP are supplied from VUSB. |
| 51 | PUR | bidirectional | USB pullup resistor pin (open drain); the voltage level at this pin invokes the default USB BSL, and a 1-MΩ resistor to ground is recommended. |
| 52 | PU.1/DM | bidirectional | General-purpose digital I/O controlled by the USB control register, or the USB data terminal DM; supplied from VUSB. |
| 53 | VBUS | power_in | USB LDO input; connect to the USB power source. |
| 54 | VUSB | power_out | USB LDO output that supplies PU.0/DP and PU.1/DM. |
| 55 | V18 | power_out | USB regulated power for internal use only; no external current loading is allowed. |
| 56 | AVSS2 | power_in | Analog ground supply. |
| 57 | P5.2/XT2IN | bidirectional | General-purpose digital I/O that becomes the input terminal for crystal oscillator XT2 in crystal or bypass mode. |
| 58 | P5.3/XT2OUT | bidirectional | General-purpose digital I/O that becomes the output terminal of crystal oscillator XT2 in crystal mode. |
| 59 | TEST/SBWTCK | input | Test mode pin that selects 4-wire JTAG operation, or the Spy-Bi-Wire input clock when Spy-Bi-Wire is active. |
| 60 | PJ.0/TDO | bidirectional | General-purpose digital I/O; the JTAG test data output port (TDO) when JTAG is in use. |
| 61 | PJ.1/TDI/TCLK | bidirectional | General-purpose digital I/O; the JTAG test data input (TDI) and test clock input (TCLK). |
| 62 | PJ.2/TMS | bidirectional | General-purpose digital I/O; the JTAG test mode select (TMS). |
| 63 | PJ.3/TCK | bidirectional | General-purpose digital I/O; the JTAG test clock (TCK). |
| 64 | RST/NMI/SBWTDIO | bidirectional | Reset input, active low (internal pullup enabled by default when configured as reset), nonmaskable interrupt input, or Spy-Bi-Wire data input/output. |
| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-64-EP(9x9) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 65 |
CAD (KiCad official)
- Symbol:
MSP430F5526IRGCR - Footprint:
Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm - 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
- 3D model files:
msp430f5526irgcr-etched.step/msp430f5526irgcr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430f5526irgcr.step/msp430f5526irgcr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (143 pp, sha256
50bf3d1f5e7fb9ee, retrieved 2026-10-12, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).