# MSP430F5521IPNR

**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)

MSP430F5521IPNR from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P6.4/CB4/A4 | bidirectional | General-purpose digital I/O with Comparator_B input CB4 and ADC12 analog input A4. |
| 2 | P6.5/CB5/A5 | bidirectional | General-purpose digital I/O with Comparator_B input CB5 and ADC12 analog input A5. |
| 3 | P6.6/CB6/A6 | bidirectional | General-purpose digital I/O with Comparator_B input CB6 and ADC12 analog input A6. |
| 4 | P6.7/CB7/A7 | bidirectional | General-purpose digital I/O with Comparator_B input CB7 and ADC12 analog input A7. |
| 5 | P7.0/CB8/A12 | bidirectional | General-purpose digital I/O with Comparator_B input CB8 and ADC12 analog input A12. |
| 6 | P7.1/CB9/A13 | bidirectional | General-purpose digital I/O with Comparator_B input CB9 and ADC12 analog input A13. |
| 7 | P7.2/CB10/A14 | bidirectional | General-purpose digital I/O with Comparator_B input CB10 and ADC12 analog input A14. |
| 8 | P7.3/CB11/A15 | bidirectional | General-purpose digital I/O with Comparator_B input CB11 and ADC12 analog input A15. |
| 9 | P5.0/A8/VREF+/VeREF+ | bidirectional | General-purpose digital I/O that also carries ADC12 analog input A8 and the ADC reference: VREF+ output or VeREF+ external reference input. |
| 10 | P5.1/A9/VREF-/VeREF- | bidirectional | General-purpose digital I/O that also carries ADC12 analog input A9 and the negative ADC reference: VREF- output or VeREF- external reference input. |
| 11 | AVCC1 | power_in | Analog power supply. |
| 12 | P5.4/XIN | bidirectional | General-purpose digital I/O; input terminal for crystal oscillator XT1 when crystal or bypass mode is selected. |
| 13 | P5.5/XOUT | bidirectional | General-purpose digital I/O; output terminal of crystal oscillator XT1 when crystal mode is selected. |
| 14 | AVSS1 | power_in | Analog ground supply. |
| 15 | P8.0 | bidirectional | General-purpose digital I/O (Port P8 is reduced to 3 bits in 80-pin packages). |
| 16 | P8.1 | bidirectional | General-purpose digital I/O (Port P8 is reduced to 3 bits in 80-pin packages). |
| 17 | P8.2 | bidirectional | General-purpose digital I/O (Port P8 is reduced to 3 bits in 80-pin packages). |
| 18 | DVCC1 | power_in | Digital power supply. |
| 19 | DVSS1 | power_in | Digital ground supply. |
| 20 | VCORE | power_out | Regulated core power supply output for internal use only; no external current loading is possible, so connect only the recommended VCORE capacitor. |
| 21 | P1.0/TA0CLK/ACLK | bidirectional | General-purpose digital I/O with port interrupt; TA0 clock input TA0CLK, or ACLK output divided by 1, 2, 4, 8, 16 or 32. |
| 22 | P1.1/TA0.0 | bidirectional | General-purpose digital I/O with port interrupt; TA0 CCR0 capture input CCI0A or compare output Out0, and BSL transmit output. |
| 23 | P1.2/TA0.1 | bidirectional | General-purpose digital I/O with port interrupt; TA0 CCR1 capture input CCI1A or compare output Out1, and BSL receive input. |
| 24 | P1.3/TA0.2 | bidirectional | General-purpose digital I/O with port interrupt; TA0 CCR2 capture input CCI2A or compare output Out2. |
| 25 | P1.4/TA0.3 | bidirectional | General-purpose digital I/O with port interrupt; TA0 CCR3 capture input CCI3A or compare output Out3. |
| 26 | P1.5/TA0.4 | bidirectional | General-purpose digital I/O with port interrupt; TA0 CCR4 capture input CCI4A or compare output Out4. |
| 27 | P1.6/TA1CLK/CBOUT | bidirectional | General-purpose digital I/O with port interrupt; TA1 clock input TA1CLK or Comparator_B output CBOUT. |
| 28 | P1.7/TA1.0 | bidirectional | General-purpose digital I/O with port interrupt; TA1 CCR0 capture input CCI0A or compare output Out0. |
| 29 | P2.0/TA1.1 | bidirectional | General-purpose digital I/O with port interrupt; TA1 CCR1 capture input CCI1A or compare output Out1. |
| 30 | P2.1/TA1.2 | bidirectional | General-purpose digital I/O with port interrupt; TA1 CCR2 capture input CCI2A or compare output Out2. |
| 31 | P2.2/TA2CLK/SMCLK | bidirectional | General-purpose digital I/O with port interrupt; TA2 clock input TA2CLK or SMCLK output. |
| 32 | P2.3/TA2.0 | bidirectional | General-purpose digital I/O with port interrupt; TA2 CCR0 capture input CCI0A or compare output Out0. |
| 33 | P2.4/TA2.1 | bidirectional | General-purpose digital I/O with port interrupt; TA2 CCR1 capture input CCI1A or compare output Out1. |
| 34 | P2.5/TA2.2 | bidirectional | General-purpose digital I/O with port interrupt; TA2 CCR2 capture input CCI2A or compare output Out2. |
| 35 | P2.6/RTCCLK/DMAE0 | bidirectional | General-purpose digital I/O with port interrupt; RTC clock output for calibration or DMA external trigger input DMAE0. |
| 36 | P2.7/UCB0STE/UCA0CLK | bidirectional | General-purpose digital I/O with port interrupt; USCI_B0 SPI slave transmit enable, or USCI_A0 clock input/output in SPI mode. |
| 37 | P3.0/UCB0SIMO/UCB0SDA | bidirectional | General-purpose digital I/O; USCI_B0 SPI slave-in/master-out, or USCI_B0 I2C data. |
| 38 | P3.1/UCB0SOMI/UCB0SCL | bidirectional | General-purpose digital I/O; USCI_B0 SPI slave-out/master-in, or USCI_B0 I2C clock. |
| 39 | P3.2/UCB0CLK/UCA0STE | bidirectional | General-purpose digital I/O; USCI_B0 SPI clock input/output, or USCI_A0 SPI slave transmit enable. |
| 40 | P3.3/UCA0TXD/UCA0SIMO | bidirectional | General-purpose digital I/O; USCI_A0 UART transmit data, or USCI_A0 SPI slave-in/master-out. |
| 41 | P3.4/UCA0RXD/UCA0SOMI | bidirectional | General-purpose digital I/O; USCI_A0 UART receive data, or USCI_A0 SPI slave-out/master-in. |
| 42 | P3.5/TB0.5 | bidirectional | General-purpose digital I/O; TB0 CCR5 capture input CCI5A or compare output Out5. |
| 43 | P3.6/TB0.6 | bidirectional | General-purpose digital I/O; TB0 CCR6 capture input CCI6A or compare output Out6. |
| 44 | P3.7/TB0OUTH/SVMOUT | bidirectional | General-purpose digital I/O; TB0OUTH switches all TB0 PWM outputs to high impedance, or SVM output SVMOUT. |
| 45 | P4.0/PM_UCB1STE/PM_UCA1CLK | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI slave transmit enable or USCI_A1 clock input/output. |
| 46 | P4.1/PM_UCB1SIMO/PM_UCB1SDA | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI slave-in/master-out or USCI_B1 I2C data. |
| 47 | P4.2/PM_UCB1SOMI/PM_UCB1SCL | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI slave-out/master-in or USCI_B1 I2C clock. |
| 48 | P4.3/PM_UCB1CLK/PM_UCA1STE | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI clock input/output or USCI_A1 SPI slave transmit enable. |
| 49 | DVSS2 | power_in | Digital ground supply. |
| 50 | DVCC2 | power_in | Digital power supply. |
| 51 | P4.4/PM_UCA1TXD/PM_UCA1SIMO | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_A1 UART transmit data or USCI_A1 SPI slave-in/master-out. |
| 52 | P4.5/PM_UCA1RXD/PM_UCA1SOMI | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_A1 UART receive data or USCI_A1 SPI slave-out/master-in. |
| 53 | P4.6/PM_NONE | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping has no secondary function. |
| 54 | P4.7/PM_NONE | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping has no secondary function. |
| 55 | P5.6/TB0.0 | bidirectional | General-purpose digital I/O; TB0 CCR0 capture input CCI0A or compare output Out0. |
| 56 | P5.7/TB0.1 | bidirectional | General-purpose digital I/O; TB0 CCR1 capture input CCI1A or compare output Out1. |
| 57 | P7.4/TB0.2 | bidirectional | General-purpose digital I/O; TB0 CCR2 capture input CCI2A or compare output Out2. |
| 58 | P7.5/TB0.3 | bidirectional | General-purpose digital I/O; TB0 CCR3 capture input CCI3A or compare output Out3. |
| 59 | P7.6/TB0.4 | bidirectional | General-purpose digital I/O; TB0 CCR4 capture input CCI4A or compare output Out4. |
| 60 | P7.7/TB0CLK/MCLK | bidirectional | General-purpose digital I/O; TB0 clock input TBCLK or MCLK output. |
| 61 | VSSU | power_in | USB PHY ground supply. |
| 62 | PU.0/DP | bidirectional | General-purpose digital I/O controlled by the USB control register; USB data terminal DP. |
| 63 | PUR | bidirectional | USB pullup resistor pin (open drain); its voltage level selects the default USB BSL, and a 1-MΩ resistor to ground is recommended. |
| 64 | PU.1/DM | bidirectional | General-purpose digital I/O controlled by the USB control register; USB data terminal DM. |
| 65 | VBUS | power_in | USB LDO input; connect to the USB power source. |
| 66 | VUSB | power_out | USB LDO output. |
| 67 | V18 | power_out | USB regulated power for internal use only; no external current loading. |
| 68 | AVSS2 | power_in | Analog ground supply. |
| 69 | P5.2/XT2IN | bidirectional | General-purpose digital I/O; input terminal for crystal oscillator XT2. |
| 70 | P5.3/XT2OUT | bidirectional | General-purpose digital I/O; output terminal of crystal oscillator XT2. |
| 71 | TEST/SBWTCK | input | Test mode pin that selects 4-wire JTAG operation; Spy-Bi-Wire input clock when Spy-Bi-Wire is active. |
| 72 | PJ.0/TDO | bidirectional | General-purpose digital I/O; JTAG test data output port. |
| 73 | PJ.1/TDI/TCLK | bidirectional | General-purpose digital I/O; JTAG test data input and test clock input. |
| 74 | PJ.2/TMS | bidirectional | General-purpose digital I/O; JTAG test mode select. |
| 75 | PJ.3/TCK | bidirectional | General-purpose digital I/O; JTAG test clock. |
| 76 | RST/NMI/SBWTDIO | bidirectional | Active-low reset input (internal pullup enabled by default when used as reset), nonmaskable interrupt input, and Spy-Bi-Wire data input/output. |
| 77 | P6.0/CB0/A0 | bidirectional | General-purpose digital I/O with Comparator_B input CB0 and ADC12 analog input A0. |
| 78 | P6.1/CB1/A1 | bidirectional | General-purpose digital I/O with Comparator_B input CB1 and ADC12 analog input A1. |
| 79 | P6.2/CB2/A2 | bidirectional | General-purpose digital I/O with Comparator_B input CB2 and ADC12 analog input A2. |
| 80 | P6.3/CB3/A3 | bidirectional | General-purpose digital I/O with Comparator_B input CB3 and ADC12 analog input A3. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-80(12x12) |
| Category | Embedded Processors & Controllers |
| Pins | 80 |

## CAD (KiCad official)

- Symbol: `MSP430F5521IPNR`
- Footprint: `Package_QFP:LQFP-80_12x12mm_P0.5mm`
- 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
- 3D model files: `msp430f5521ipnr-etched.step` / `msp430f5521ipnr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430f5521ipnr.step` / `msp430f5521ipnr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](http://www.ti.com/cn/lit/gpn/msp430f5524) (143 pp, sha256 `50bf3d1f5e7fb9ee`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/msp430f5521ipnr-datasheet.pdf)