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MSP430F5510IRGCR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), QFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersmsp430f5510irgcrfactory-2.0.0extractor-text

Verified MSP430F5510IRGCR

by Ray · last 5 Nov 2026 · 1 record · files match
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Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 65 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: MSP430F5510IRGCR · QFN-64-EP(9x9) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 134-page datasheet
  • ✓distributor: lcsc C181301, digikey 296-27650-2-ND, mouser 595-MSP430F5510IRGCR
  • ✓family: QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-b4t___fb/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ msp430f5510irgcr.kicad_sym✓ msp430f5510irgcr.kicad_mod✓ msp430f5510irgcr.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 4h ago
viewers msp430f5510irgcr: viewers · Ray 4h ago
msp430f5510irgcr-etched.glb Publish 0.1.0 · Ray 4h ago
msp430f5510irgcr-etched.step msp430f5510irgcr: factory component page (tier=mfr) · Ray 4h ago
msp430f5510irgcr-hero.glb msp430f5510irgcr: hero GLB from the etched model (keeps the MPN mark) · Ray 4h ago
msp430f5510irgcr-hero.overlay.json Publish 0.1.0 · Ray 4h ago
msp430f5510irgcr.glb Publish 0.1.0 · Ray 4h ago
msp430f5510irgcr.kicad_mod Publish 0.1.0 · Ray 4h ago
msp430f5510irgcr.kicad_sym Publish 0.1.0 · Ray 4h ago
msp430f5510irgcr.lbr Publish 0.1.0 · Ray 4h ago
msp430f5510irgcr.step Publish 0.1.0 · Ray 4h ago
package.json Publish 0.1.0 · Ray 4h ago
page.json Set visibility: public · Ray 4h ago
README.md Publish 0.1.0 · Ray 4h ago
verification.json Verified: Published by the parts factory: tier mfr, 65 pins · Ray 4h ago

MSP430F5510IRGCR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · QFN-64-EP(9x9)

MSP430F5510IRGCR from Texas Instruments, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P6.0/CB0/A0 bidirectional General-purpose digital I/O that can also serve as Comparator_B input CB0 or ADC analog input A0 (A0 not available on F5503 to F5500 devices).
2 P6.1/CB1/A1 bidirectional General-purpose digital I/O that can also serve as Comparator_B input CB1 or ADC analog input A1 (A1 not available on F5503 to F5500 devices).
3 P6.2/CB2/A2 bidirectional General-purpose digital I/O that can also serve as Comparator_B input CB2 or ADC analog input A2 (A2 not available on F5503 to F5500 devices).
4 P6.3/CB3/A3 bidirectional General-purpose digital I/O that can also serve as Comparator_B input CB3 or ADC analog input A3 (A3 not available on F5503 to F5500 devices).
5 P6.4/CB4/A4 bidirectional General-purpose digital I/O that can also serve as Comparator_B input CB4 or ADC analog input A4 (not available on PT and RGZ packages).
6 P6.5/CB5/A5 bidirectional General-purpose digital I/O that can also serve as Comparator_B input CB5 or ADC analog input A5 (not available on PT and RGZ packages).
7 P6.6/CB6/A6 bidirectional General-purpose digital I/O that can also serve as Comparator_B input CB6 or ADC analog input A6 (not available on PT and RGZ packages).
8 P6.7/CB7/A7 bidirectional General-purpose digital I/O that can also serve as Comparator_B input CB7 or ADC analog input A7 (not available on PT and RGZ packages).
9 P5.0/A8/VeREF+ bidirectional General-purpose digital I/O that can also serve as ADC analog input A8 or external ADC reference input VeREF+.
10 P5.1/A9/VeREF- bidirectional General-purpose digital I/O that can also serve as ADC analog input A9 or negative external ADC reference VeREF-.
11 AVCC1 power_in Analog power supply.
12 P5.4/XIN input General-purpose digital I/O that serves as the input terminal for crystal oscillator XT1 in crystal or bypass mode.
13 P5.5/XOUT output General-purpose digital I/O that serves as the output terminal of crystal oscillator XT1 in crystal mode.
14 AVSS1 power_in Analog ground supply.
15 DVCC1 power_in Digital power supply.
16 DVSS1 power_in Digital ground supply.
17 VCORE power_out Regulated core power supply output for internal use only, with no external current loading; connect only the recommended capacitor CVCORE.
18 P1.0/TA0CLK/ACLK bidirectional General-purpose digital I/O with port interrupt; also TA0 clock input TA0CLK or ACLK output divided by 1, 2, 4, 8, 16, or 32.
19 P1.1/TA0.0 bidirectional General-purpose digital I/O with port interrupt; also TA0 CCR0 capture input CCI0A or compare output Out0, and BSL transmit output.
20 P1.2/TA0.1 bidirectional General-purpose digital I/O with port interrupt; also TA0 CCR1 capture input CCI1A or compare output Out1, and BSL receive input.
21 P1.3/TA0.2 bidirectional General-purpose digital I/O with port interrupt; also TA0 CCR2 capture input CCI2A or compare output Out2.
22 P1.4/TA0.3 bidirectional General-purpose digital I/O with port interrupt; also TA0 CCR3 capture input CCI3A or compare output Out3.
23 P1.5/TA0.4 bidirectional General-purpose digital I/O with port interrupt; also TA0 CCR4 capture input CCI4A or compare output Out4.
24 P1.6/TA1CLK/CBOUT bidirectional General-purpose digital I/O with port interrupt; also TA1 clock input TA1CLK or Comparator_B output CBOUT.
25 P1.7/TA1.0 bidirectional General-purpose digital I/O with port interrupt; also TA1 CCR0 capture input CCI0A or compare output Out0.
26 P2.0/TA1.1 bidirectional General-purpose digital I/O with port interrupt; also TA1 CCR1 capture input CCI1A or compare output Out1.
27 P2.1/TA1.2 bidirectional General-purpose digital I/O with port interrupt; also TA1 CCR2 capture input CCI2A or compare output Out2.
28 P2.2/TA2CLK/SMCLK bidirectional General-purpose digital I/O with port interrupt; also TA2 clock input TA2CLK or SMCLK output.
29 P2.3/TA2.0 bidirectional General-purpose digital I/O with port interrupt; also TA2 CCR0 capture input CCI0A or compare output Out0.
30 P2.4/TA2.1 bidirectional General-purpose digital I/O with port interrupt; also TA2 CCR1 capture input CCI1A or compare output Out1.
31 P2.5/TA2.2 bidirectional General-purpose digital I/O with port interrupt; also TA2 CCR2 capture input CCI2A or compare output Out2.
32 P2.6/RTCCLK/DMAE0 bidirectional General-purpose digital I/O with port interrupt; also RTC clock output for calibration or DMA external trigger input DMAE0.
33 P2.7/UCB0STE/UCA0CLK bidirectional General-purpose digital I/O with port interrupt; also USCI_B0 SPI slave transmit enable or USCI_A0 clock input/output.
34 P3.0/UCB0SIMO/UCB0SDA bidirectional General-purpose digital I/O; also USCI_B0 SPI slave-in/master-out or I2C data UCB0SDA.
35 P3.1/UCB0SOMI/UCB0SCL bidirectional General-purpose digital I/O; also USCI_B0 SPI slave-out/master-in or I2C clock UCB0SCL.
36 P3.2/UCB0CLK/UCA0STE bidirectional General-purpose digital I/O; also USCI_B0 SPI clock input/output or USCI_A0 SPI slave transmit enable.
37 P3.3/UCA0TXD/UCA0SIMO bidirectional General-purpose digital I/O; also USCI_A0 UART transmit data or SPI slave-in/master-out.
38 P3.4/UCA0RXD/UCA0SOMI bidirectional General-purpose digital I/O; also USCI_A0 UART receive data or SPI slave-out/master-in.
39 DVSS2 power_in Digital ground supply.
40 DVCC2 power_in Digital power supply.
41 P4.0/PM_UCB1STE/PM_UCA1CLK bidirectional General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI slave transmit enable or USCI_A1 clock input/output.
42 P4.1/PM_UCB1SIMO/PM_UCB1SDA bidirectional General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI slave-in/master-out or I2C data.
43 P4.2/PM_UCB1SOMI/PM_UCB1SCL bidirectional General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI slave-out/master-in or I2C clock.
44 P4.3/PM_UCB1CLK/PM_UCA1STE bidirectional General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI clock input/output or USCI_A1 SPI slave transmit enable.
45 P4.4/PM_UCA1TXD/PM_UCA1SIMO bidirectional General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_A1 UART transmit data or SPI slave-in/master-out.
46 P4.5/PM_UCA1RXD/PM_UCA1SOMI bidirectional General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_A1 UART receive data or SPI slave-out/master-in.
47 P4.6/PM_NONE bidirectional General-purpose digital I/O with reconfigurable port mapping; default mapping has no secondary function.
48 P4.7/PM_NONE bidirectional General-purpose digital I/O with reconfigurable port mapping; default mapping has no secondary function.
49 VSSU power_in USB PHY ground supply.
50 PU.0/DP bidirectional General-purpose digital I/O controlled by the USB control register; also USB data terminal DP.
51 PUR bidirectional USB pullup resistor pin (open drain); recommended 1-MΩ resistor to ground, and its voltage level selects the default USB BSL.
52 PU.1/DM bidirectional General-purpose digital I/O controlled by the USB control register; also USB data terminal DM.
53 VBUS power_in USB LDO input; connect to the USB power source.
54 VUSB power_out USB LDO output.
55 V18 power_out USB regulated power for internal use only, with no external current loading.
56 AVSS2 power_in Analog ground supply.
57 P5.2/XT2IN input General-purpose digital I/O that serves as the input terminal for crystal oscillator XT2 in crystal or bypass mode.
58 P5.3/XT2OUT output General-purpose digital I/O that serves as the output terminal of crystal oscillator XT2 in crystal mode.
59 TEST/SBWTCK input Test mode pin that selects digital I/O on the JTAG pins; also Spy-Bi-Wire input clock.
60 PJ.0/TDO bidirectional General-purpose digital I/O; also JTAG test data output port TDO.
61 PJ.1/TDI/TCLK bidirectional General-purpose digital I/O; also JTAG test data input TDI and test clock input TCLK.
62 PJ.2/TMS bidirectional General-purpose digital I/O; also JTAG test mode select TMS.
63 PJ.3/TCK bidirectional General-purpose digital I/O; also JTAG test clock TCK.
64 RST/NMI/SBWTDIO bidirectional Reset input, active low, with internal pullup enabled by default when configured as reset; also nonmaskable interrupt input and Spy-Bi-Wire data input/output.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-64-EP(9x9)
Category Embedded Processors & Controllers
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage during program execution and flash programming (PMMCOREVx = 0) VCC 1.8 3.6 V AVCC = DVCC, PMMCOREVx = 0 19
Supply voltage during program execution and flash programming (PMMCOREVx = 0, 1) VCC 2 3.6 V AVCC = DVCC, PMMCOREVx = 0, 1 19
Supply voltage during program execution and flash programming (PMMCOREVx = 0, 1, 2) VCC 2.2 3.6 V AVCC = DVCC, PMMCOREVx = 0, 1, 2 19
Supply voltage during program execution and flash programming (PMMCOREVx = 0, 1, 2, 3) VCC 2.4 3.6 V AVCC = DVCC, PMMCOREVx = 0, 1, 2, 3 19
Supply voltage during USB operation, USB PLL disabled (PMMCOREVx = 0) VCC,USB 1.8 3.6 V USB_EN = 1, UPLLEN = 0, PMMCOREVx = 0 19
Supply voltage during USB operation, USB PLL disabled (PMMCOREVx = 0, 1) VCC,USB 2 3.6 V USB_EN = 1, UPLLEN = 0, PMMCOREVx = 0, 1 19
Supply voltage during USB operation, USB PLL disabled (PMMCOREVx = 0, 1, 2) VCC,USB 2.2 3.6 V USB_EN = 1, UPLLEN = 0, PMMCOREVx = 0, 1, 2 19
Supply voltage during USB operation, USB PLL disabled (PMMCOREVx = 0, 1, 2, 3) VCC,USB 2.4 3.6 V USB_EN = 1, UPLLEN = 0, PMMCOREVx = 0, 1, 2, 3 19
Supply voltage during USB operation, USB PLL enabled (PMMCOREVx = 2) VCC,USB 2.2 3.6 V USB_EN = 1, UPLLEN = 1, PMMCOREVx = 2 19
Supply voltage during USB operation, USB PLL enabled (PMMCOREVx = 2, 3) VCC,USB 2.4 3.6 V USB_EN = 1, UPLLEN = 1, PMMCOREVx = 2, 3 19
Processor frequency (maximum MCLK frequency) fSYSTEM 0 8 MHz PMMCOREVx = 0, 1.8 V ≤ VCC ≤ 3.6 V 20
Processor frequency (maximum MCLK frequency) fSYSTEM 0 12 MHz PMMCOREVx = 1, 2.0 V ≤ VCC ≤ 3.6 V 20
Processor frequency (maximum MCLK frequency) fSYSTEM 0 20 MHz PMMCOREVx = 2, 2.2 V ≤ VCC ≤ 3.6 V 20
Processor frequency (maximum MCLK frequency) fSYSTEM 0 25 MHz PMMCOREVx = 3, 2.4 V ≤ VCC ≤ 3.6 V 20
Minimum processor frequency for USB operation fSYSTEM_USB 1.5 MHz 20
Operating free-air temperature I version TA -40 85 °C I version 19
Operating junction temperature I version TJ -40 85 °C I version 19
Voltage applied at VCC to VSS VCC -0.3 4.1 V 19
Voltage applied to any pin (excluding VCORE, VBUS, V18) -0.3 V maximum printed as VCC + 0.3 V 19
Diode current at any device pin -2 2 mA 19
Maximum junction temperature TJ 95 °C 19
Storage temperature Tstg -55 150 °C 19
Positive-going input threshold voltage VIT+ 0.8 1.4 V VCC = 1.8 V 24
Positive-going input threshold voltage VIT+ 1.5 2.1 V VCC = 3 V 24
Negative-going input threshold voltage VIT- 0.45 1 V VCC = 1.8 V 24
Negative-going input threshold voltage VIT- 0.75 1.65 V VCC = 3 V 24
Input voltage hysteresis (VIT+, VIT-) Vhys 0.3 0.85 V VCC = 1.8 V 24
Input voltage hysteresis (VIT+, VIT-) Vhys 0.4 1 V VCC = 3 V 24
Pullup or pulldown resistor RPull 20 35 50 kΩ For pullup: VIN = VSS; For pulldown: VIN = VCC 24
High-impedance leakage current Ilkg(Px.y) -50 50 nA VCC = 1.8 V, 3 V 24
High-level output voltage VOH 2.4 V VUSB = 3.3 V ±10%, IOH = -25 mA 45
Low-level output voltage VOL 0.4 V VUSB = 3.3 V ±10%, IOL = 25 mA 45
High-level input voltage VIH 2 V VUSB = 3.3 V ±10% 45
Low-level input voltage VIL 0.8 V VUSB = 3.3 V ±10% 45
High-level output voltage D+, D- single ended VOH 2.8 3.6 V USB 2.0 load conditions 47
Low-level output voltage D+, D- single ended VOL 0 0.3 V USB 2.0 load conditions 47
D+, D- impedance Z(DRV) 28 44 Ω Including external series resistor of 27 Ω 47
Rise time tRISE 4 20 ns Full speed, differential, CL = 50 pF, 10%/90%, Rpu on D+ 47
Fall time tFALL 4 20 ns Full speed, differential, CL = 50 pF, 10%/90%, Rpu on D+ 47
Static SE input logic low level VIL 0.8 V 47
Static SE input logic high level VIH 2 V 47
USB bus voltage VBUS 3.76 5.5 V Normal operation 47
USB LDO output voltage tolerance VUSB -9 9 % USB LDO output voltage 3.3 V ±9% 47
USB LDO current overload detection IDET 60 100 mA 47
Pullup resistance of PUR terminal RPUR 70 110 150 Ω 47
XT2 oscillator crystal frequency, mode 0 fXT2,HF0 4 8 MHz XT2DRIVEx = 0, XT2BYPASS = 0 29
XT2 oscillator crystal frequency, mode 1 fXT2,HF1 8 16 MHz XT2DRIVEx = 1, XT2BYPASS = 0 29
XT2 oscillator crystal frequency, mode 2 fXT2,HF2 16 24 MHz XT2DRIVEx = 2, XT2BYPASS = 0 29
XT2 oscillator crystal frequency, mode 3 fXT2,HF3 24 32 MHz XT2DRIVEx = 3, XT2BYPASS = 0 29
XT2 oscillator logic-level square-wave input frequency, bypass mode fXT2,HF,SW 0.7 32 MHz XT2BYPASS = 1 29
XT1 oscillator logic-level square-wave input frequency, LF mode fXT1,LF,SW 10 32.768 50 kHz XTS = 0, XT1BYPASS = 1 28
VLO frequency fVLO 6 9.4 14 kHz Measured at ACLK, 1.8 V to 3.6 V 30
REFO absolute tolerance calibrated, full temperature range -3.5 3.5 % Full temperature range, 1.8 V to 3.6 V 30
REFO absolute tolerance calibrated, TA = 25°C -1.5 1.5 % TA = 25°C, 3 V 30
Port output frequency (with load), VCC = 1.8 V fPx.y 16 MHz VCC = 1.8 V, PMMCOREVx = 0 25
Port output frequency (with load), VCC = 3 V fPx.y 25 MHz VCC = 3 V, PMMCOREVx = 3 25
Thermal resistance junction-to-ambient, still air, VQFN (RGC) θJA 30 °C/W Still air, JEDEC High-K board 23
Thermal resistance junction-to-case (top), VQFN (RGC) θJC(TOP) 15.6 °C/W 23
Thermal resistance junction-to-case (bottom), VQFN (RGC) θJC(BOTTOM) 1.6 °C/W 23
Thermal resistance junction-to-board, VQFN (RGC) θJB 8.9 °C/W 23

CAD (KiCad official)

  • Symbol: MSP430F5510IRGCR
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: msp430f5510irgcr-etched.step / msp430f5510irgcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430f5510irgcr.step / msp430f5510irgcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (134 pp, sha256 00704c373f824b5a, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF