# MSP430F5504IRGZT

**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · VQFN-48-EP(7x7)

MSP430F5504IRGZT from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P6.0/A0 | bidirectional | General-purpose digital I/O with ADC analog input A0 (CB0 comparator input not available on F5504). |
| 2 | P6.1/A1 | bidirectional | General-purpose digital I/O with ADC analog input A1 (CB1 comparator input not available on F5504). |
| 3 | P6.2/A2 | bidirectional | General-purpose digital I/O with ADC analog input A2 (CB2 comparator input not available on F5504). |
| 4 | P6.3/A3 | bidirectional | General-purpose digital I/O with ADC analog input A3 (CB3 comparator input not available on F5504). |
| 5 | P5.0/A8/VeREF+ | bidirectional | General-purpose digital I/O, ADC analog input A8, and input for an external ADC reference voltage VeREF+. |
| 6 | P5.1/A9/VeREF- | bidirectional | General-purpose digital I/O, ADC analog input A9, and negative terminal for an externally provided ADC reference VeREF-. |
| 7 | AVCC1 | power_in | Analog power supply. |
| 8 | P5.4/XIN | bidirectional | General-purpose digital I/O and input terminal for crystal oscillator XT1. |
| 9 | P5.5/XOUT | bidirectional | General-purpose digital I/O and output terminal of crystal oscillator XT1. |
| 10 | AVSS1 | power_in | Analog ground supply. |
| 11 | DVCC1 | power_in | Digital power supply. |
| 12 | DVSS1 | power_in | Digital ground supply. |
| 13 | VCORE | power_out | Regulated core power supply output for internal use only, with no external current loading; connect only to the recommended capacitor CVCORE. |
| 14 | P1.0/TA0CLK/ACLK | bidirectional | General-purpose digital I/O with port interrupt, TA0 clock input, or ACLK output divided by 1, 2, 4, 8, 16, or 32. |
| 15 | P1.1/TA0.0 | bidirectional | General-purpose digital I/O with port interrupt, TA0 CCR0 capture/compare, and BSL transmit output. |
| 16 | P1.2/TA0.1 | bidirectional | General-purpose digital I/O with port interrupt, TA0 CCR1 capture/compare, and BSL receive input. |
| 17 | P1.3/TA0.2 | bidirectional | General-purpose digital I/O with port interrupt and TA0 CCR2 capture/compare. |
| 18 | P1.4/TA0.3 | bidirectional | General-purpose digital I/O with port interrupt and TA0 CCR3 capture/compare. |
| 19 | P1.5/TA0.4 | bidirectional | General-purpose digital I/O with port interrupt and TA0 CCR4 capture/compare. |
| 20 | P1.6/TA1CLK | bidirectional | General-purpose digital I/O with port interrupt and TA1 clock signal TA1CLK input. |
| 21 | P1.7/TA1.0 | bidirectional | General-purpose digital I/O with port interrupt and TA1 CCR0 capture/compare. |
| 22 | P2.0/TA1.1 | bidirectional | General-purpose digital I/O with port interrupt and TA1 CCR1 capture/compare. |
| 23 | PJ.0/TDO | bidirectional | General-purpose digital I/O and JTAG test data output port. |
| 24 | PJ.1/TDI/TCLK | bidirectional | General-purpose digital I/O, JTAG test data input, and test clock input. |
| 25 | PJ.2/TMS | bidirectional | General-purpose digital I/O and JTAG test mode select. |
| 26 | PJ.3/TCK | bidirectional | General-purpose digital I/O and JTAG test clock. |
| 27 | DVSS2 | power_in | Digital ground supply. |
| 28 | DVCC2 | power_in | Digital power supply. |
| 29 | P4.0/PM_UCB1STE/PM_UCA1CLK | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI slave transmit enable or USCI_A1 clock. |
| 30 | P4.1/PM_UCB1SIMO/PM_UCB1SDA | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI slave in/master out or I2C data. |
| 31 | P4.2/PM_UCB1SOMI/PM_UCB1SCL | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 SPI slave out/master in or I2C clock. |
| 32 | P4.3/PM_UCB1CLK/PM_UCA1STE | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_B1 clock or USCI_A1 SPI slave transmit enable. |
| 33 | P4.4/PM_UCA1TXD/PM_UCA1SIMO | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_A1 UART transmit data or SPI slave in/master out. |
| 34 | P4.5/PM_UCA1RXD/PM_UCA1SOMI | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping is USCI_A1 UART receive data or SPI slave out/master in. |
| 35 | P4.6/PM_NONE | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping has no secondary function. |
| 36 | P4.7/PM_NONE | bidirectional | General-purpose digital I/O with reconfigurable port mapping; default mapping has no secondary function. |
| 37 | VSSU | power_in | USB PHY ground supply. |
| 38 | PU.0/DP | bidirectional | General-purpose digital I/O controlled by the USB control register and USB data terminal DP. |
| 39 | PUR | bidirectional | USB pullup resistor pin (open drain); the voltage level is used to invoke the default USB BSL, with a recommended 1-MΩ resistor to ground. |
| 40 | PU.1/DM | bidirectional | General-purpose digital I/O controlled by the USB control register and USB data terminal DM. |
| 41 | VBUS | power_in | USB LDO input; connect to USB power source. |
| 42 | VUSB | power_out | USB LDO output. |
| 43 | V18 | power_out | USB regulated power for internal use only, with no external current loading. |
| 44 | AVSS2 | power_in | Analog ground supply. |
| 45 | P5.2/XT2IN | bidirectional | General-purpose digital I/O and input terminal for crystal oscillator XT2. |
| 46 | P5.3/XT2OUT | bidirectional | General-purpose digital I/O and output terminal of crystal oscillator XT2. |
| 47 | TEST/SBWTCK | input | Test mode pin used to select digital I/O on JTAG pins and as Spy-Bi-Wire input clock. |
| 48 | RST/NMI/SBWTDIO | bidirectional | Reset input, active low (internal pullup enabled by default when configured as reset), nonmaskable interrupt input, and Spy-Bi-Wire data input/output. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VCC to VSS | VCC | -0.3 |  | 4.1 | V | Voltage applied at VCC to VSS | 19 |
| Voltage applied to any pin |  | -0.3 |  |  | V | Maximum printed as VCC + 0.3 (excluding VCORE, VBUS, V18) | 19 |
| Diode current at any device pin |  | -2 |  | 2 | mA | Diode current at any device pin | 19 |
| Maximum junction temperature | TJ |  |  | 95 | °C |  | 19 |
| Storage temperature | Tstg | -55 |  | 150 | °C |  | 19 |
| Supply voltage during program execution and flash programming (PMMCOREVx = 0) | VCC | 1.8 |  | 3.6 | V | AVCC = DVCC, PMMCOREVx = 0 | 19 |
| Supply voltage during program execution and flash programming (PMMCOREVx = 3) | VCC | 2.4 |  | 3.6 | V | AVCC = DVCC, PMMCOREVx = 0, 1, 2, 3 | 19 |
| Capacitor at VCORE | CVCORE |  | 470 |  | nF |  | 19 |
| Operating free-air temperature (I version) | TA | -40 |  | 85 | °C | I version | 19 |
| Operating junction temperature (I version) | TJ | -40 |  | 85 | °C | I version | 19 |
| Processor frequency (maximum MCLK frequency), PMMCOREVx = 0 | fSYSTEM | 0 |  | 8 | MHz | PMMCOREVx = 0, 1.8 V ≤ VCC ≤ 3.6 V | 20 |
| Processor frequency (maximum MCLK frequency), PMMCOREVx = 3 | fSYSTEM | 0 |  | 25 | MHz | PMMCOREVx = 3, 2.4 V ≤ VCC ≤ 3.6 V | 20 |
| Junction-to-ambient thermal resistance, still air, VQFN (RGZ) | θJA |  | 28.6 |  | °C/W | Still air, VQFN (RGZ) | 23 |
| Junction-to-case (top) thermal resistance, VQFN (RGZ) | θJC(TOP) |  | 14.4 |  | °C/W | VQFN (RGZ) | 23 |
| Junction-to-case (bottom) thermal resistance, VQFN (RGZ) | θJC(BOTTOM) |  | 1.6 |  | °C/W | VQFN (RGZ) | 23 |
| Junction-to-board thermal resistance, VQFN (RGZ) | θJB |  | 5.5 |  | °C/W | VQFN (RGZ) | 23 |
| Active mode supply current into VCC, flash execution, 1 MHz | IAM |  | 0.25 | 0.27 | mA | Flash execution, 3 V, PMMCOREVx = 0, fDCO = fMCLK = fSMCLK = 1 MHz | 21 |
| Positive-going input threshold voltage | VIT+ | 0.8 |  | 1.4 | V | VCC = 1.8 V | 24 |
| Positive-going input threshold voltage | VIT+ | 1.5 |  | 2.1 | V | VCC = 3 V | 24 |
| Negative-going input threshold voltage | VIT- | 0.45 |  | 1 | V | VCC = 1.8 V | 24 |
| Negative-going input threshold voltage | VIT- | 0.75 |  | 1.65 | V | VCC = 3 V | 24 |
| Pullup or pulldown resistor | RPull | 20 | 35 | 50 | kΩ | For pullup: VIN = VSS; for pulldown: VIN = VCC | 24 |

## CAD (KiCad official)

- Symbol: `MSP430F5504IRGZT`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files: `msp430f5504irgzt-etched.step` / `msp430f5504irgzt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430f5504irgzt.step` / `msp430f5504irgzt.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/msp430f5504.pdf) (134 pp, sha256 `00704c373f824b5a`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/msp430f5504irgzt-datasheet.pdf)