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MSP430F5503IRGZR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSP430F5503IRGZR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-48-EP(7x7)

MSP430F5503IRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P6.0/CB0 bidirectional General-purpose digital I/O and Comparator_B input CB0.
2 P6.1/CB1 bidirectional General-purpose digital I/O and Comparator_B input CB1.
3 P6.2/CB2 bidirectional General-purpose digital I/O and Comparator_B input CB2.
4 P6.3/CB3 bidirectional General-purpose digital I/O and Comparator_B input CB3.
5 P5.0 bidirectional General-purpose digital I/O.
6 P5.1 bidirectional General-purpose digital I/O.
7 AVCC1 power_in Analog power supply.
8 P5.4/XIN bidirectional General-purpose digital I/O or XT1 crystal oscillator input terminal.
9 P5.5/XOUT bidirectional General-purpose digital I/O or XT1 crystal oscillator output terminal.
10 AVSS1 power_in Analog ground supply.
11 DVCC1 power_in Digital power supply.
12 DVSS1 power_in Digital ground supply.
13 VCORE power_out Regulated core power supply output for internal use only; no external current loading permitted.
14 P1.0/TA0CLK/ACLK bidirectional General-purpose digital I/O with port interrupt, TA0 clock signal input, or ACLK output.
15 P1.1/TA0.0 bidirectional General-purpose digital I/O with port interrupt or TA0 CCR0 capture/compare.
16 P1.2/TA0.1 bidirectional General-purpose digital I/O with port interrupt or TA0 CCR1 capture/compare.
17 P1.3/TA0.2 bidirectional General-purpose digital I/O with port interrupt or TA0 CCR2 capture/compare.
18 P1.4/TA0.3 bidirectional General-purpose digital I/O with port interrupt or TA0 CCR3 capture/compare.
19 P1.5/TA0.4 bidirectional General-purpose digital I/O with port interrupt or TA0 CCR4 capture/compare.
20 P1.6/TA1CLK/CBOUT bidirectional General-purpose digital I/O with port interrupt, TA1 clock input, or Comparator_B output.
21 P1.7/TA1.0 bidirectional General-purpose digital I/O with port interrupt or TA1 CCR0 capture/compare.
22 P2.0/TA1.1 bidirectional General-purpose digital I/O with port interrupt or TA1 CCR1 capture/compare.
23 PJ.0/TDO bidirectional General-purpose digital I/O or JTAG test data output.
24 PJ.1/TDI/TCLK bidirectional General-purpose digital I/O, JTAG test data input, or test clock input.
25 PJ.2/TMS bidirectional General-purpose digital I/O or JTAG test mode select.
26 PJ.3/TCK bidirectional General-purpose digital I/O or JTAG test clock.
27 DVSS2 power_in Digital ground supply.
28 DVCC2 power_in Digital power supply.
29 P4.0/PM_UCB1STE/PM_UCA1CLK bidirectional General-purpose digital I/O with reconfigurable port mapping to USCI_B1 SPI slave transmit enable or USCI_A1 clock.
30 P4.1/PM_UCB1SIMO/PM_UCB1SDA bidirectional General-purpose digital I/O with reconfigurable port mapping to USCI_B1 slave in/master out or I2C data.
31 P4.2/PM_UCB1SOMI/PM_UCB1SCL bidirectional General-purpose digital I/O with reconfigurable port mapping to USCI_B1 slave out/master in or I2C clock.
32 P4.3/PM_UCB1CLK/PM_UCA1STE bidirectional General-purpose digital I/O with reconfigurable port mapping to USCI_B1 clock or USCI_A1 SPI slave transmit enable.
33 P4.4/PM_UCA1TXD/PM_UCA1SIMO bidirectional General-purpose digital I/O with reconfigurable port mapping to USCI_A1 UART transmit or SPI slave in/master out.
34 P4.5/PM_UCA1RXD/PM_UCA1SOMI bidirectional General-purpose digital I/O with reconfigurable port mapping to USCI_A1 UART receive or SPI slave out/master in.
35 P4.6/PM_NONE bidirectional General-purpose digital I/O with reconfigurable port mapping.
36 P4.7/PM_NONE bidirectional General-purpose digital I/O with reconfigurable port mapping.
37 VSSU power_in USB PHY ground supply.
38 PU.0/DP bidirectional General-purpose digital I/O controlled by USB control register or USB data terminal DP.
39 PUR output USB pullup resistor pin with open-drain output; recommended 1-MΩ resistor to ground for invoking default USB bootloader.
40 PU.1/DM bidirectional General-purpose digital I/O controlled by USB control register or USB data terminal DM.
41 VBUS power_in USB LDO input connected to USB power source.
42 VUSB power_out USB LDO output.
43 V18 power_out USB regulated 1.8V power for internal use only; no external current loading permitted.
44 AVSS2 power_in Analog ground supply.
45 P5.2/XT2IN bidirectional General-purpose digital I/O or XT2 crystal oscillator input terminal.
46 P5.3/XT2OUT bidirectional General-purpose digital I/O or XT2 crystal oscillator output terminal.
47 TEST/SBWTCK input Test mode pin to select digital I/O on JTAG pins or Spy-By-Wire input clock.
48 RST/NMI/SBWTDIO bidirectional Reset input (active low), nonmaskable interrupt input, or Spy-By-Wire data input/output.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Embedded Processors & Controllers
Pins 49

CAD (KiCad official)

  • Symbol: MSP430F5503IRGZR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: msp430f5503irgzr-etched.step / msp430f5503irgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430f5503irgzr.step / msp430f5503irgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (134 pp, sha256 39e075da0f1e3944, retrieved 2026-09-27, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF