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MSP430F5438AIPZR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430F5438AIPZR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)
MSP430F5438AIPZR from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P6.4/A4 | bidirectional | General-purpose I/O configurable as input or output; analog input channel A4 for 12-bit ADC |
| 2 | P6.5/A5 | bidirectional | General-purpose I/O configurable as input or output; analog input channel A5 for 12-bit ADC |
| 3 | P6.6/A6 | bidirectional | General-purpose I/O configurable as input or output; analog input channel A6 for 12-bit ADC |
| 4 | P6.7/A7 | bidirectional | General-purpose I/O configurable as input or output; analog input channel A7 for 12-bit ADC |
| 5 | P7.4/A12 | bidirectional | General-purpose I/O configurable as input or output; analog input channel A12 for 12-bit ADC |
| 6 | P7.5/A13 | bidirectional | General-purpose I/O configurable as input or output; analog input channel A13 for 12-bit ADC |
| 7 | P7.6/A14 | bidirectional | General-purpose I/O configurable as input or output; analog input channel A14 for 12-bit ADC |
| 8 | P7.7/A15 | bidirectional | General-purpose I/O configurable as input or output; analog input channel A15 for 12-bit ADC |
| 9 | P5.0/A8/VREF+/VeREF+ | bidirectional | General-purpose I/O; ADC input channel A8; VREF+ output or external reference voltage input to ADC |
| 10 | P5.1/A9/VREF-/VeREF- | bidirectional | General-purpose I/O; ADC input channel A9; VREF- negative terminal for ADC reference voltage |
| 11 | AVCC | power_in | Analog power supply for ADC and reference circuitry |
| 12 | AVSS | power_in | Analog ground supply for ADC and reference circuitry |
| 13 | P7.0/XIN | bidirectional | General-purpose I/O configurable as input or output; input terminal for XT1 crystal oscillator |
| 14 | P7.1/XOUT | bidirectional | General-purpose I/O configurable as input or output; output terminal for XT1 crystal oscillator |
| 15 | DVSS1 | power_in | Digital ground supply |
| 16 | DVCC1 | power_in | Digital power supply |
| 17 | P1.0/TA0CLK/ACLK | bidirectional | General-purpose I/O with port interrupt; TA0 clock input or ACLK output |
| 18 | P1.1/TA0.0 | bidirectional | General-purpose I/O with port interrupt; Timer_A0 capture/compare register 0 input/output |
| 19 | P1.2/TA0.1 | bidirectional | General-purpose I/O with port interrupt; Timer_A0 capture/compare register 1 input/output |
| 20 | P1.3/TA0.2 | bidirectional | General-purpose I/O with port interrupt; Timer_A0 capture/compare register 2 input/output |
| 21 | P1.4/TA0.3 | bidirectional | General-purpose I/O with port interrupt; Timer_A0 capture/compare register 3 input/output |
| 22 | P1.5/TA0.4 | bidirectional | General-purpose I/O with port interrupt; Timer_A0 capture/compare register 4 input/output |
| 23 | P1.6/SMCLK | bidirectional | General-purpose I/O with port interrupt; SMCLK output |
| 24 | P1.7 | bidirectional | General-purpose I/O with port interrupt capability |
| 25 | P2.0/TA1CLK/MCLK | bidirectional | General-purpose I/O with port interrupt; TA1 clock input or MCLK output |
| 26 | P2.1/TA1.0 | bidirectional | General-purpose I/O with port interrupt; Timer_A1 capture/compare register 0 input/output |
| 27 | P2.2/TA1.1 | bidirectional | General-purpose I/O with port interrupt; Timer_A1 capture/compare register 1 input/output |
| 28 | P2.3/TA1.2 | bidirectional | General-purpose I/O with port interrupt; Timer_A1 capture/compare register 2 input/output |
| 29 | P2.4/RTCCLK | bidirectional | General-purpose I/O with port interrupt; RTC clock output |
| 30 | P2.5 | bidirectional | General-purpose I/O with port interrupt capability |
| 31 | P2.6/ACLK | bidirectional | General-purpose I/O with port interrupt; ACLK output |
| 32 | P2.7/ADC12CLK/DMAE0 | bidirectional | General-purpose I/O with port interrupt; ADC conversion clock output or DMA external trigger input |
| 33 | P3.0/UCB0STE/UCA0CLK | bidirectional | General-purpose I/O; USCI_B0 SPI slave transmit enable or USCI_A0 clock input/output |
| 34 | P3.1/UCB0SIMO/UCB0SDA | bidirectional | General-purpose I/O; USCI_B0 SPI slave in master out or I2C data line |
| 35 | P3.2/UCB0SOMI/UCB0SCL | bidirectional | General-purpose I/O; USCI_B0 SPI slave out master in or I2C clock line |
| 36 | P3.3/UCB0CLK/UCA0STE | bidirectional | General-purpose I/O; USCI_B0 SPI clock or USCI_A0 SPI slave transmit enable |
| 37 | DVSS3 | power_in | Digital ground supply |
| 38 | DVCC3 | power_in | Digital power supply |
| 39 | P3.4/UCA0TXD/UCA0SIMO | bidirectional | General-purpose I/O; USCI_A0 UART transmit data or SPI slave in master out |
| 40 | P3.5/UCA0RXD/UCA0SOMI | bidirectional | General-purpose I/O; USCI_A0 UART receive data or SPI slave out master in |
| 41 | P3.6/UCB1STE/UCA1CLK | bidirectional | General-purpose I/O; USCI_B1 SPI slave transmit enable or USCI_A1 clock input/output |
| 42 | P3.7/UCB1SIMO/UCB1SDA | bidirectional | General-purpose I/O; USCI_B1 SPI slave in master out or I2C data line |
| 43 | P4.0/TB0.0 | bidirectional | General-purpose I/O; Timer_B0 capture/compare register 0 input/output |
| 44 | P4.1/TB0.1 | bidirectional | General-purpose I/O; Timer_B0 capture/compare register 1 input/output |
| 45 | P4.2/TB0.2 | bidirectional | General-purpose I/O; Timer_B0 capture/compare register 2 input/output |
| 46 | P4.3/TB0.3 | bidirectional | General-purpose I/O; Timer_B0 capture/compare register 3 input/output |
| 47 | P4.4/TB0.4 | bidirectional | General-purpose I/O; Timer_B0 capture/compare register 4 input/output |
| 48 | P4.5/TB0.5 | bidirectional | General-purpose I/O; Timer_B0 capture/compare register 5 input/output |
| 49 | P4.6/TB0.6 | bidirectional | General-purpose I/O; Timer_B0 capture/compare register 6 input/output |
| 50 | P4.7/TB0CLK/SMCLK | bidirectional | General-purpose I/O; TB0 clock input or SMCLK output |
| 51 | P5.4/UCB1SOMI/UCB1SCL | bidirectional | General-purpose I/O; USCI_B1 SPI slave out master in or I2C clock line |
| 52 | P5.5/UCB1CLK/UCA1STE | bidirectional | General-purpose I/O; USCI_B1 SPI clock or USCI_A1 SPI slave transmit enable |
| 53 | P5.6/UCA1TXD/UCA1SIMO | bidirectional | General-purpose I/O; USCI_A1 UART transmit data or SPI slave in master out |
| 54 | P5.7/UCA1RXD/UCA1SOMI | bidirectional | General-purpose I/O; USCI_A1 UART receive data or SPI slave out master in |
| 55 | P7.2/TB0OUTH/SVMOUT | bidirectional | General-purpose I/O; sets Timer_B0 PWM outputs to high impedance or provides SVM output |
| 56 | P7.3/TA1.2 | bidirectional | General-purpose I/O; Timer_A1 capture/compare register 2 input/output |
| 57 | P8.0/TA0.0 | bidirectional | General-purpose I/O; Timer_A0 capture/compare register 0 alternate input/output |
| 58 | P8.1/TA0.1 | bidirectional | General-purpose I/O; Timer_A0 capture/compare register 1 alternate input/output |
| 59 | P8.2/TA0.2 | bidirectional | General-purpose I/O; Timer_A0 capture/compare register 2 alternate input/output |
| 60 | P8.3/TA0.3 | bidirectional | General-purpose I/O; Timer_A0 capture/compare register 3 alternate input/output |
| 61 | P8.4/TA0.4 | bidirectional | General-purpose I/O; Timer_A0 capture/compare register 4 alternate input/output |
| 62 | VCORE | power_out | Regulated core voltage output for internal use only with no external current loading |
| 63 | DVSS2 | power_in | Digital ground supply |
| 64 | DVCC2 | power_in | Digital power supply |
| 65 | P8.5/TA1.0 | bidirectional | General-purpose I/O; Timer_A1 capture/compare register 0 alternate input/output |
| 66 | P8.6/TA1.1 | bidirectional | General-purpose I/O; Timer_A1 capture/compare register 1 alternate input/output |
| 67 | P8.7 | bidirectional | General-purpose I/O configurable as input or output |
| 68 | P9.0/UCB2STE/UCA2CLK | bidirectional | General-purpose I/O; USCI_B2 SPI slave transmit enable or USCI_A2 clock input/output |
| 69 | P9.1/UCB2SIMO/UCB2SDA | bidirectional | General-purpose I/O; USCI_B2 SPI slave in master out or I2C data line |
| 70 | P9.2/UCB2SOMI/UCB2SCL | bidirectional | General-purpose I/O; USCI_B2 SPI slave out master in or I2C clock line |
| 71 | P9.3/UCB2CLK/UCA2STE | bidirectional | General-purpose I/O; USCI_B2 SPI clock or USCI_A2 SPI slave transmit enable |
| 72 | P9.4/UCA2TXD/UCA2SIMO | bidirectional | General-purpose I/O; USCI_A2 UART transmit data or SPI slave in master out |
| 73 | P9.5/UCA2RXD/UCA2SOMI | bidirectional | General-purpose I/O; USCI_A2 UART receive data or SPI slave out master in |
| 74 | P9.6 | bidirectional | General-purpose I/O configurable as input or output |
| 75 | P9.7 | bidirectional | General-purpose I/O configurable as input or output |
| 76 | P10.0/UCB3STE/UCA3CLK | bidirectional | General-purpose I/O; USCI_B3 SPI slave transmit enable or USCI_A3 clock input/output |
| 77 | P10.1/UCB3SIMO/UCB3SDA | bidirectional | General-purpose I/O; USCI_B3 SPI slave in master out or I2C data line |
| 78 | P10.2/UCB3SOMI/UCB3SCL | bidirectional | General-purpose I/O; USCI_B3 SPI slave out master in or I2C clock line |
| 79 | P10.3/UCB3CLK/UCA3STE | bidirectional | General-purpose I/O; USCI_B3 SPI clock or USCI_A3 SPI slave transmit enable |
| 80 | P10.4/UCA3TXD/UCA3SIMO | bidirectional | General-purpose I/O; USCI_A3 UART transmit data or SPI slave in master out |
| 81 | P10.5/UCA3RXD/UCA3SOMI | bidirectional | General-purpose I/O; USCI_A3 UART receive data or SPI slave out master in |
| 82 | P10.6 | bidirectional | General-purpose I/O configurable as input or output |
| 83 | P10.7 | bidirectional | General-purpose I/O configurable as input or output |
| 84 | P11.0/ACLK | bidirectional | General-purpose I/O; ACLK output |
| 85 | P11.1/MCLK | bidirectional | General-purpose I/O; MCLK output |
| 86 | P11.2/SMCLK | bidirectional | General-purpose I/O; SMCLK output |
| 87 | DVCC4 | power_in | Digital power supply |
| 88 | DVSS4 | power_in | Digital ground supply |
| 89 | P5.2/XT2IN | bidirectional | General-purpose I/O configurable as input or output; input terminal for XT2 crystal oscillator |
| 90 | P5.3/XT2OUT | bidirectional | General-purpose I/O configurable as input or output; output terminal for XT2 crystal oscillator |
| 91 | TEST/SBWTCK | input | Test mode pin to select four-wire JTAG operation or Spy-Bi-Wire clock input |
| 92 | PJ.0/TDO | bidirectional | General-purpose I/O configurable as input or output; JTAG test data output port |
| 93 | PJ.1/TDI/TCLK | bidirectional | General-purpose I/O configurable as input or output; JTAG test data input or test clock input |
| 94 | PJ.2/TMS | bidirectional | General-purpose I/O configurable as input or output; JTAG test mode select |
| 95 | PJ.3/TCK | bidirectional | General-purpose I/O configurable as input or output; JTAG test clock |
| 96 | RST/NMI/SBWTDIO | bidirectional | Reset input (active low) or nonmaskable interrupt input; Spy-Bi-Wire data input/output when activated |
| 97 | P6.0/A0 | bidirectional | General-purpose I/O configurable as input or output; analog input channel A0 for 12-bit ADC |
| 98 | P6.1/A1 | bidirectional | General-purpose I/O configurable as input or output; analog input channel A1 for 12-bit ADC |
| 99 | P6.2/A2 | bidirectional | General-purpose I/O configurable as input or output; analog input channel A2 for 12-bit ADC |
| 100 | P6.3/A3 | bidirectional | General-purpose I/O configurable as input or output; analog input channel A3 for 12-bit ADC |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |
CAD (KiCad official)
- Symbol:
MSP430F5438AIPZR - Footprint:
Package_QFP:LQFP-100_14x14mm_P0.5mm - 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files:
msp430f5438aipzr-etched.step/msp430f5438aipzr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430f5438aipzr.step/msp430f5438aipzr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (125 pp, sha256
5d97e3b015facd10, retrieved 2026-09-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).