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MSP430F5342IRGZT

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Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSP430F5342IRGZT

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-48-EP(7x7)

MSP430F5342IRGZT from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P6.3/CB3/A3 bidirectional General-purpose digital I/O pin; supports Comparator_B input CB3 and ADC analog input A3 for ADC12.
2 P6.4/CB4/A4 bidirectional General-purpose digital I/O pin; supports Comparator_B input CB4 and ADC analog input A4 for ADC12.
3 P6.5/CB5/A5 bidirectional General-purpose digital I/O pin; supports Comparator_B input CB5 and ADC analog input A5 for ADC12.
4 P5.0/A8/VREF+/VeREF+ bidirectional General-purpose digital I/O pin; supports ADC reference voltage output (VREF+) or external reference input (VeREF+) and ADC analog input A8.
5 P5.1/A9/VREF-/VeREF- bidirectional General-purpose digital I/O pin; supports ADC negative reference terminal (VREF-/VeREF-) and ADC analog input A9.
6 AVCC1 power_in Analog power supply input for ADC and reference circuits; recommended voltage 1.8 V to 3.6 V.
7 P5.4/XIN bidirectional General-purpose digital I/O pin; supports XT1 crystal oscillator (32 kHz) input terminal.
8 P5.5/XOUT bidirectional General-purpose digital I/O pin; supports XT1 crystal oscillator (32 kHz) output terminal.
9 AVSS1 power_in Analog ground supply; reference potential for analog circuits.
10 DVCC1 power_in Digital power supply input for core logic and digital I/O; recommended voltage 1.8 V to 3.6 V.
11 DVSS1 power_in Digital ground supply; reference potential for digital circuits.
12 VCORE power_out Regulated core power supply output from internal voltage regulator; internal use only with no external current loading.
13 P1.0/TA0CLK/ACLK bidirectional General-purpose digital I/O pin with port interrupt; supports Timer_A0 clock input (TA0CLK) or ACLK clock output.
14 P1.1/TA0.0 bidirectional General-purpose digital I/O pin with port interrupt; supports Timer_A0 CCR0 capture/compare output or BSL transmit.
15 P1.2/TA0.1 bidirectional General-purpose digital I/O pin with port interrupt; supports Timer_A0 CCR1 capture/compare output or BSL receive input.
16 P1.3/TA0.2 bidirectional General-purpose digital I/O pin with port interrupt; supports Timer_A0 CCR2 capture/compare.
17 P1.4/TA0.3 bidirectional General-purpose digital I/O pin with port interrupt; supports Timer_A0 CCR3 capture/compare.
18 P1.5/TA0.4 bidirectional General-purpose digital I/O pin with port interrupt; supports Timer_A0 CCR4 capture/compare.
19 P1.6/TA1CLK/CBOUT bidirectional General-purpose digital I/O pin with port interrupt; supports Timer_A1 clock input (TA1CLK) or Comparator_B output.
20 P1.7/TA1.0 bidirectional General-purpose digital I/O pin with port interrupt; supports Timer_A1 CCR0 capture/compare.
21 P2.7/UCB0STE/UCA0CLK bidirectional General-purpose digital I/O pin with port interrupt; supports USCI_B0 SPI slave transmit enable or USCI_A0 clock.
22 P3.0/UCB0SIMO/UCB0SDA bidirectional General-purpose digital I/O pin; supports USCI_B0 SPI master-in-slave-out or I2C data (open-drain).
23 P3.1/UCB0SOMI/UCB0SCL bidirectional General-purpose digital I/O pin; supports USCI_B0 SPI slave-out-master-in or I2C clock (open-drain).
24 P3.2/UCB0CLK/UCA0STE bidirectional General-purpose digital I/O pin; supports USCI_B0 clock or USCI_A0 SPI slave transmit enable.
25 P3.3/UCA0TXD/UCA0SIMO bidirectional General-purpose digital I/O pin; supports USCI_A0 UART transmit or SPI master-in-slave-out.
26 P3.4/UCA0RXD/UCA0SOMI bidirectional General-purpose digital I/O pin; supports USCI_A0 UART receive or SPI slave-out-master-in.
27 P4.0/PM_UCB1STE/PM_UCA1CLK bidirectional General-purpose digital I/O pin with port mapping; supports mapped USCI_B1 STE or USCI_A1 clock functions.
28 P4.1/PM_UCB1SIMO/PM_UCB1SDA bidirectional General-purpose digital I/O pin with port mapping; supports mapped USCI_B1 master-in-slave-out or I2C data.
29 P4.2/PM_UCB1SOMI/PM_UCB1SCL bidirectional General-purpose digital I/O pin with port mapping; supports mapped USCI_B1 slave-out-master-in or I2C clock.
30 P4.3/PM_UCB1CLK/PM_UCA1STE bidirectional General-purpose digital I/O pin with port mapping; supports mapped USCI_B1 clock or USCI_A1 STE.
31 DVSS2 power_in Digital ground supply; reference potential for digital circuits.
32 DVCC2 power_in Digital power supply input for core logic and digital I/O; recommended voltage 1.8 V to 3.6 V.
33 P4.4/PM_UCA1TXD/PM_UCA1SIMO bidirectional General-purpose digital I/O pin with port mapping; supports mapped USCI_A1 UART transmit or SPI functions.
34 P4.5/PM_UCA1RXD/PM_UCA1SOMI bidirectional General-purpose digital I/O pin with port mapping; supports mapped USCI_A1 UART receive or SPI functions.
35 P4.6/PM_NONE bidirectional General-purpose digital I/O pin with port mapping; no secondary function mapped by default.
36 P4.7/PM_NONE bidirectional General-purpose digital I/O pin with port mapping; no secondary function mapped by default.
37 P5.7/TB0.1 bidirectional General-purpose digital I/O pin; supports Timer_B0 CCR1 capture/compare.
38 DVSS3 power_in Digital ground supply; reference potential for digital circuits.
39 P5.2/XT2IN bidirectional General-purpose digital I/O pin; supports XT2 crystal oscillator (up to 32 MHz) input terminal.
40 P5.3/XT2OUT bidirectional General-purpose digital I/O pin; supports XT2 crystal oscillator (up to 32 MHz) output terminal.
41 TEST/SBWTCK input Test pin and Spy-Bi-Wire clock input; used for device programming and debugging via SBW protocol.
42 PJ.0/TDO output JTAG test data output; can be configured as general-purpose digital I/O for GPIO applications.
43 PJ.1/TDI/TCLK input JTAG test data input or test clock for programming; can be configured as general-purpose digital I/O.
44 PJ.2/TMS input JTAG test mode select input; can be configured as general-purpose digital I/O.
45 PJ.3/TCK input JTAG test clock input; can be configured as general-purpose digital I/O.
46 RST/NMI/SBWTDIO input Device reset input and non-maskable interrupt input; also serves as Spy-Bi-Wire data I/O (bidirectional in SBW mode).
47 P6.1/CB1/A1 bidirectional General-purpose digital I/O pin; supports Comparator_B input CB1 and ADC analog input A1 for ADC12.
48 P6.2/CB2/A2 bidirectional General-purpose digital I/O pin; supports Comparator_B input CB2 and ADC analog input A2 for ADC12.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Embedded Processors & Controllers
Pins 49

CAD (KiCad official)

  • Symbol: MSP430F5342IRGZT
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: msp430f5342irgzt-etched.step / msp430f5342irgzt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430f5342irgzt.step / msp430f5342irgzt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (100 pp, sha256 72f515f6a8312e6c, retrieved 2026-10-05, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF