# MSP430F5249IRGCR

**Texas Instruments** · Microcontroller Units (MCUs/MPUs/SOCs) · VQFN-64-EP(9x9)

MSP430F5249IRGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P6.0/A0/CB0 | bidirectional | General-purpose digital I/O with Comparator_B input CB0 and ADC10 analog input A0; output driver and input buffer are disabled when CBPD.0 is set or when CB0 is selected as an input. |
| 2 | P6.1/A1/CB1 | bidirectional | General-purpose digital I/O with Comparator_B input CB1 and ADC10 analog input A1; output driver and input buffer are disabled when CBPD.1 is set or when CB1 is selected as an input. |
| 3 | P6.2/A2/CB2 | bidirectional | General-purpose digital I/O with Comparator_B input CB2 and ADC10 analog input A2; output driver and input buffer are disabled when CBPD.2 is set or when CB2 is selected as an input. |
| 4 | P6.3/A3/CB3 | bidirectional | General-purpose digital I/O with Comparator_B input CB3 and ADC10 analog input A3; output driver and input buffer are disabled when CBPD.3 is set or when CB3 is selected as an input. |
| 5 | P6.4/CB4/A4 | bidirectional | General-purpose digital I/O with Comparator_B input CB4 and analog input A4 for the ADC. |
| 6 | P6.5/CB5/A5 | bidirectional | General-purpose digital I/O with Comparator_B input CB5 and analog input A5 for the ADC. |
| 7 | P6.6/CB6/A6 | bidirectional | General-purpose digital I/O with Comparator_B input CB6 and analog input A6 for the ADC; the datasheet marks this function as not available on all device types. |
| 8 | P6.7/CB7/A7 | bidirectional | General-purpose digital I/O with Comparator_B input CB7 and analog input A7 for the ADC; the datasheet marks this function as not available on all device types. |
| 9 | P5.0/A8/VeREF+ | bidirectional | General-purpose digital I/O with ADC analog input A8, and input for an external ADC reference voltage VeREF+ when selected. |
| 10 | P5.1/A9/VeREF- | bidirectional | General-purpose digital I/O with ADC analog input A9, and negative terminal VeREF- for an externally applied ADC reference voltage when selected. |
| 11 | AVCC | power_in | Analog power supply. |
| 12 | P5.4/XIN | bidirectional | General-purpose digital I/O that serves as the input terminal for crystal oscillator XT1 when P5SEL.4 is set. |
| 13 | P5.5/XOUT | bidirectional | General-purpose digital I/O that serves as the output terminal of crystal oscillator XT1 in crystal mode; usable as general-purpose I/O in bypass mode. |
| 14 | AVSS | power_in | Analog ground supply. |
| 15 | DVCC | power_in | Digital power supply. |
| 16 | DVSS | power_in | Digital ground supply. |
| 17 | VCORE | power_out | Regulated core power supply output for internal use only; no external current loading is possible and only the recommended capacitor CVCORE should be connected. |
| 18 | P1.0/TA0CLK/ACLK | bidirectional | General-purpose digital I/O with port interrupt, TA0 clock input TA0CLK, or ACLK output divided by 1, 2, 4, 8, 16, or 32. |
| 19 | P1.1/TA0.0 | bidirectional | General-purpose digital I/O with port interrupt, TA0 CCR0 capture input CCI0A or compare output Out0, and BSL transmit output. |
| 20 | P1.2/TA0.1 | bidirectional | General-purpose digital I/O with port interrupt, TA0 CCR1 capture input CCI1A or compare output Out1, and BSL receive input. |
| 21 | P1.3/TA0.2 | bidirectional | General-purpose digital I/O with port interrupt, TA0 CCR2 capture input CCI2A or compare output Out2. |
| 22 | P1.4/TA0.3 | bidirectional | General-purpose digital I/O with TA0 CCR3 capture input CCI3A or compare output TA0.3. |
| 23 | P1.5/TA0.4 | bidirectional | General-purpose digital I/O with TA0 CCR4 capture input CCI4A or compare output TA0.4. |
| 24 | P1.6/TA1CLK/CBOUT | bidirectional | General-purpose digital I/O with TA1 clock input TA1CLK or Comparator_B output CBOUT. |
| 25 | P1.7/TA1.0 | bidirectional | General-purpose digital I/O with TA1 CCR0 capture input TA1.CCI0A or compare output TA1.0. |
| 26 | P2.0/TA1.1 | bidirectional | General-purpose digital I/O with TA1 CCR1 capture input TA1.CCI1A or compare output TA1.1. |
| 27 | P2.1/TA1.2 | bidirectional | General-purpose digital I/O with TA1 CCR2 capture input TA1.CCI2A or compare output TA1.2. |
| 28 | P2.2/TA2CLK/SMCLK | bidirectional | General-purpose digital I/O with TA2 clock input TA2CLK or SMCLK output. |
| 29 | P2.3/TA2.0 | bidirectional | General-purpose digital I/O with TA2 CCR0 capture input TA2.CCI0A or compare output TA2.0. |
| 30 | P2.4/TA2.1 | bidirectional | General-purpose digital I/O with TA2 CCR1 capture input TA2.CCI1A or compare output TA2.1. |
| 31 | P2.5/TA2.2 | bidirectional | General-purpose digital I/O with TA2 CCR2 capture input TA2.CCI2A or compare output TA2.2. |
| 32 | P2.6/RTCCLK/DMAE0 | bidirectional | General-purpose digital I/O with DMA external trigger input DMAE0 or RTCCLK output. |
| 33 | P2.7/UCB0STE/UCA0CLK | bidirectional | General-purpose digital I/O with USCI_B0 SPI slave transmit enable or USCI_A0 clock input/output; UCA0CLK takes precedence over UCB0STE when both are selected. |
| 34 | P3.0/UCB0SIMO/UCB0SDA | bidirectional | General-purpose digital I/O with USCI_B0 SPI slave-in/master-out or I2C data UCB0SDA; when I2C is selected the output drives only logic 0 to VSS. |
| 35 | P3.1/UCB0SOMI/UCB0SCL | bidirectional | General-purpose digital I/O with USCI_B0 SPI slave-out/master-in or I2C clock UCB0SCL; when I2C is selected the output drives only logic 0 to VSS. |
| 36 | P3.2/UCB0CLK/UCA0STE | bidirectional | General-purpose digital I/O with USCI_B0 clock input/output UCB0CLK or USCI_A0 SPI slave transmit enable UCA0STE; UCB0CLK takes precedence over UCA0STE. |
| 37 | P3.3/UCA0TXD/UCA0SIMO | bidirectional | General-purpose digital I/O with USCI_A0 UART transmit output UCA0TXD or SPI slave-in/master-out UCA0SIMO. |
| 38 | P3.4/UCA0RXD/UCA0SOMI | bidirectional | General-purpose digital I/O with USCI_A0 UART receive input UCA0RXD or SPI slave-out/master-in UCA0SOMI. |
| 39 | DVSS | power_in | Digital ground supply. |
| 40 | DVCC | power_in | Digital power supply. |
| 41 | P4.0/PM_UCB1STE/PM_UCA1CLK | bidirectional | General-purpose digital I/O whose secondary function is selected by the port mapping controller (default mapping USCI_B1 SPI slave transmit enable or USCI_A1 clock input/output). |
| 42 | P4.1/PM_UCB1SIMO/PM_UCB1SDA | bidirectional | General-purpose digital I/O whose secondary function is selected by the port mapping controller (default mapping USCI_B1 SPI slave-in/master-out or I2C data). |
| 43 | P4.2/PM_UCB1SOMI/PM_UCB1SCL | bidirectional | General-purpose digital I/O whose secondary function is selected by the port mapping controller (default mapping USCI_B1 SPI slave-out/master-in or I2C clock). |
| 44 | P4.3/PM_UCB1CLK/PM_UCA1STE | bidirectional | General-purpose digital I/O whose secondary function is selected by the port mapping controller (default mapping USCI_B1 clock input/output or USCI_A1 SPI slave transmit enable). |
| 45 | P4.4/PM_UCA1TXD/PM_UCA1SIMO | bidirectional | General-purpose digital I/O whose secondary function is selected by the port mapping controller (default mapping USCI_A1 UART TXD or SPI slave-in/master-out). |
| 46 | P4.5/PM_UCA1RXD/PM_UCA1SOMI | bidirectional | General-purpose digital I/O whose secondary function is selected by the port mapping controller (default mapping USCI_A1 UART RXD or SPI slave-out/master-in). |
| 47 | P4.6/PM_NONE | bidirectional | General-purpose digital I/O; default port mapping is PM_NONE, which connects no secondary function (input tied to DVSS). |
| 48 | P4.7/PM_NONE | bidirectional | General-purpose digital I/O; default port mapping is PM_NONE, which connects no secondary function (input tied to DVSS). |
| 49 | P7.0/TB0.0 | bidirectional | General-purpose digital I/O with Timer_B TB0 CCR0 capture input TB0.CCI0A or compare output TB0.0. |
| 50 | P7.1/TB0.1 | bidirectional | General-purpose digital I/O with Timer_B TB0 CCR1 capture input TB0.CCI1A or compare output TB0.1. |
| 51 | P7.2/TB0.2 | bidirectional | General-purpose digital I/O with Timer_B TB0 CCR2 capture input TB0.CCI2A or compare output TB0.2. |
| 52 | P7.3/TB0.3 | bidirectional | General-purpose digital I/O with Timer_B TB0 CCR3 capture input TB0.CCI3A or compare output TB0.3. |
| 53 | P7.4/TB0.4 | bidirectional | General-purpose digital I/O with Timer_B TB0 CCR4 capture input TB0.CCI4A or compare output TB0.4. |
| 54 | P7.5/TB0.5 | bidirectional | General-purpose digital I/O with Timer_B TB0 CCR5 capture input TB0.CCI5A or compare output TB0.5. |
| 55 | NC | unconnected | Terminal labeled NC in the pin diagram with no function listed. |
| 56 | RST/NMI | input | Reset (RST) or non-maskable interrupt (NMI) input, listed among the Schmitt-trigger inputs in Section 5.7. |
| 57 | P5.2/XT2IN | bidirectional | General-purpose digital I/O that becomes the XT2 high-frequency oscillator input XT2IN in crystal mode or bypass mode when P5SEL.2 is set. |
| 58 | P5.3/XT2OUT | bidirectional | General-purpose digital I/O that becomes the XT2 crystal output XT2OUT in crystal mode (P5SEL.3 set, XT2BYPASS clear); usable as general-purpose I/O in bypass mode. |
| 59 | TEST/SBWTCK | input | Spy-Bi-Wire clock input (SBWTCK) for development tools and device programmers, shared with the TEST function. |
| 60 | PJ.0/TDO | bidirectional | Port J bit PJ.0 whose JTAG TDO function is driven by the JTAG module, with direction controlled by the JTAG module. |
| 61 | PJ.1/TDI/TCLK | bidirectional | Port J bit PJ.1 used as JTAG TDI/TCLK input, with direction controlled by the JTAG module and pullups activated automatically in JTAG mode. |
| 62 | PJ.2/TMS | bidirectional | Port J bit PJ.2 used as JTAG TMS input, with direction controlled by the JTAG module and pullups activated automatically in JTAG mode. |
| 63 | PJ.3/TCK | bidirectional | Port J bit PJ.3 used as JTAG TCK input, with direction controlled by the JTAG module and pullups activated automatically in JTAG mode. |
| 64 | RSTDVCC/SBWTDIO | bidirectional | Spy-Bi-Wire data input/output (SBWTDIO) for development tools and device programmers; the pin name also lists the RSTDVCC reset function, with limits given in Table 4-1 outside the supplied pages. |
| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-64-EP(9x9) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 65 |

## CAD (KiCad official)

- Symbol: `MSP430F5249IRGCR`
- Footprint: `Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm`
- 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
- 3D model files: `msp430f5249irgcr-etched.step` / `msp430f5249irgcr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430f5249irgcr.step` / `msp430f5249irgcr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430f5239) (114 pp, sha256 `9acee9f0b4b7514f`, retrieved 2026-10-11, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/msp430f5249irgcr-datasheet.pdf)