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MSP430F5247IRGCR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSP430F5247IRGCR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-64(9x9)

MSP430F5247IRGCR from Texas Instruments, in a VQFN-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P6.0/A0/CB0 bidirectional General-purpose digital I/O P6.0, also ADC10 analog input A0 and Comparator_B input CB0, where selecting CB0 disables the pin's output driver and input buffer.
2 P6.1/A1/CB1 bidirectional General-purpose digital I/O P6.1, also ADC10 analog input A1 and Comparator_B input CB1, where selecting CB1 disables the pin's output driver and input buffer.
3 P6.2/A2/CB2 bidirectional General-purpose digital I/O P6.2, also ADC10 analog input A2 and Comparator_B input CB2, where selecting CB2 disables the pin's output driver and input buffer.
4 P6.3/A3/CB3 bidirectional General-purpose digital I/O P6.3, also ADC10 analog input A3 and Comparator_B input CB3, where selecting CB3 disables the pin's output driver and input buffer.
5 P6.4/CB4/A4 bidirectional General-purpose digital I/O; Comparator_B input CB4 and analog input A4 for the ADC.
6 P6.5/CB5/A5 bidirectional General-purpose digital I/O; Comparator_B input CB5 and analog input A5 for the ADC.
7 P6.6/CB6/A6 bidirectional General-purpose digital I/O; Comparator_B input CB6 and analog input A6 for the ADC.
8 P6.7/CB7/A7 bidirectional General-purpose digital I/O; Comparator_B input CB7 and analog input A7 for the ADC.
9 P5.0/A8/VeREF+ bidirectional General-purpose digital I/O; analog input A8 and input for an external ADC reference voltage VeREF+, where setting P5SEL.0 disables the output driver and input Schmitt trigger.
10 P5.1/A9/VeREF- bidirectional General-purpose digital I/O; analog input A9 and negative terminal VeREF- for an external ADC reference, where setting P5SEL.1 disables the output driver and input Schmitt trigger.
11 AVCC power_in Analog power supply.
12 P5.4/XIN bidirectional General-purpose digital I/O; input terminal for crystal oscillator XT1 in crystal or bypass mode (selected with P5SEL.4 and XT1BYPASS).
13 P5.5/XOUT bidirectional General-purpose digital I/O; output terminal of crystal oscillator XT1 in crystal mode (usable as GPIO in bypass mode).
14 AVSS power_in Analog ground supply.
15 DVCC power_in Digital power supply.
16 DVSS power_in Digital ground supply.
17 VCORE power_out Regulated core power supply output for internal use only; no external current loading is possible and it should only be connected to the recommended CVCORE capacitor.
18 P1.0/TA0CLK/ACLK bidirectional General-purpose digital I/O with port interrupt; TA0 clock input TA0CLK or ACLK output divided by 1, 2, 4, 8, 16, or 32.
19 P1.1/TA0.0 bidirectional General-purpose digital I/O with port interrupt; TA0 CCR0 capture input CCI0A or compare output Out0, and BSL transmit output.
20 P1.2/TA0.1 bidirectional General-purpose digital I/O with port interrupt; TA0 CCR1 capture input CCI1A or compare output Out1, and BSL receive input.
21 P1.3/TA0.2 bidirectional General-purpose digital I/O with port interrupt; TA0 CCR2 capture input CCI2A or compare output Out2.
22 P1.4/TA0.3 bidirectional General-purpose digital I/O with port interrupt; TA0 CCR3 capture input CCI3A or compare output Out3.
23 P1.5/TA0.4 bidirectional General-purpose digital I/O with port interrupt; TA0 CCR4 capture input CCI4A or compare output Out4.
24 P1.6/TA1CLK/CBOUT bidirectional General-purpose digital I/O with port interrupt; TA1 clock input TA1CLK or Comparator_B output CBOUT.
25 P1.7/TA1.0 bidirectional General-purpose digital I/O with port interrupt; TA1 CCR0 capture input CCI0A or compare output TA1.0.
26 P2.0/TA1.1 bidirectional General-purpose digital I/O with port interrupt; TA1 CCR1 capture input CCI1A or compare output TA1.1.
27 P2.1/TA1.2 bidirectional General-purpose digital I/O with port interrupt; TA1 CCR2 capture input CCI2A or compare output TA1.2.
28 P2.2/TA2CLK/SMCLK bidirectional General-purpose digital I/O with port interrupt; TA2 clock input TA2CLK or SMCLK output.
29 P2.3/TA2.0 bidirectional General-purpose digital I/O with port interrupt; TA2 CCR0 capture input CCI0A or compare output TA2.0.
30 P2.4/TA2.1 bidirectional General-purpose digital I/O with port interrupt; TA2 CCR1 capture input CCI1A or compare output TA2.1.
31 P2.5/TA2.2 bidirectional General-purpose digital I/O with port interrupt; TA2 CCR2 capture input CCI2A or compare output TA2.2.
32 P2.6/RTCCLK/DMAE0 bidirectional General-purpose digital I/O with port interrupt; DMA external trigger input DMAE0 or RTCCLK output, selected by P2SEL.
33 P2.7/UCB0STE/UCA0CLK bidirectional General-purpose digital I/O; USCI_B0 SPI transmit enable or USCI_A0 clock input/output, where UCA0CLK takes precedence over UCB0STE.
34 P3.0/UCB0SIMO/UCB0SDA bidirectional General-purpose digital I/O; USCI_B0 SPI slave-in/master-out or I2C data line (direction controlled by USCI).
35 P3.1/UCB0SOMI/UCB0SCL bidirectional General-purpose digital I/O; USCI_B0 SPI slave-out/master-in or I2C clock line, which drives only logical 0 to VSS in I2C mode.
36 P3.2/UCB0CLK/UCA0STE bidirectional General-purpose digital I/O; USCI_B0 clock input/output or USCI_A0 SPI transmit enable, where UCB0CLK takes precedence over UCA0STE.
37 P3.3/UCA0TXD/UCA0SIMO bidirectional General-purpose digital I/O; USCI_A0 UART transmit output or USCI_A0 SPI slave-in/master-out.
38 P3.4/UCA0RXD/UCA0SOMI bidirectional General-purpose digital I/O; USCI_A0 UART receive input or USCI_A0 SPI slave-out/master-in.
39 DVSS power_in Digital ground supply.
40 DVCC power_in Digital power supply.
41 P4.0/PM_UCB1STE/PM_UCA1CLK bidirectional General-purpose digital I/O; port-mapped secondary function (default USCI_B1 SPI transmit enable or USCI_A1 clock) selected via P4MAP0, with mapping values 1 to 30 enabling the function.
42 P4.1/PM_UCB1SIMO/PM_UCB1SDA bidirectional General-purpose digital I/O; port-mapped USCI_B1 SPI slave-in/master-out or I2C data (default mapping) selected via P4MAP1.
43 P4.2/PM_UCB1SOMI/PM_UCB1SCL bidirectional General-purpose digital I/O; port-mapped USCI_B1 SPI slave-out/master-in or I2C clock (default mapping) selected via P4MAP2.
44 P4.3/PM_UCB1CLK/PM_UCA1STE bidirectional General-purpose digital I/O; port-mapped USCI_B1 clock input/output or USCI_A1 SPI transmit enable (default mapping) selected via P4MAP3.
45 P4.4/PM_UCA1TXD/PM_UCA1SIMO bidirectional General-purpose digital I/O; port-mapped USCI_A1 UART transmit or SPI slave-in/master-out (default mapping) selected via P4MAP4.
46 P4.5/PM_UCA1RXD/PM_UCA1SOMI bidirectional General-purpose digital I/O; port-mapped USCI_A1 UART receive or SPI slave-out/master-in (default mapping) selected via P4MAP5.
47 P4.6/PM_NONE bidirectional General-purpose digital I/O; port mapping value PM_NONE connects the mapped secondary function to DVSS.
48 P4.7/PM_NONE bidirectional General-purpose digital I/O; port mapping value PM_NONE connects the mapped secondary function to DVSS.
49 P7.0/TB0.0 bidirectional General-purpose digital I/O; Timer_B TB0 CCR0 capture input CCI0A or compare output TB0.0.
50 P7.1/TB0.1 bidirectional General-purpose digital I/O; Timer_B TB0 CCR1 capture input CCI1A or compare output TB0.1.
51 P7.2/TB0.2 bidirectional General-purpose digital I/O; Timer_B TB0 CCR2 capture input CCI2A or compare output TB0.2.
52 P7.3/TB0.3 bidirectional General-purpose digital I/O; Timer_B TB0 CCR3 capture input CCI3A or compare output TB0.3.
53 P7.4/TB0.4 bidirectional General-purpose digital I/O; Timer_B TB0 CCR4 capture input CCI4A or compare output TB0.4.
54 P7.5/TB0.5 bidirectional General-purpose digital I/O; Timer_B TB0 CCR5 capture input CCI5A or compare output TB0.5.
55 NC unconnected Not connected; listed as NC in the RGC pinout.
56 RST/NMI input Device reset or non-maskable interrupt input (Schmitt-trigger input).
57 P5.2/XT2IN bidirectional General-purpose digital I/O; XT2 high-frequency crystal input in crystal or bypass mode (selected with P5SEL.2 and XT2BYPASS).
58 P5.3/XT2OUT bidirectional General-purpose digital I/O; XT2 crystal output in crystal mode, usable as GPIO in bypass mode.
59 TEST/SBWTCK input Test mode pin; Spy-Bi-Wire clock input (SBWTCK) for development tools and programmers.
60 PJ.0/TDO bidirectional General-purpose digital I/O PJ.0 or JTAG test data output TDO.
61 PJ.1/TDI/TCLK bidirectional General-purpose digital I/O PJ.1 or JTAG test data input TDI / test clock TCLK.
62 PJ.2/TMS bidirectional General-purpose digital I/O PJ.2 or JTAG test mode select TMS; pullups are automatically activated on TMS in JTAG mode.
63 PJ.3/TCK bidirectional General-purpose digital I/O PJ.3 or JTAG test clock TCK; pullups are automatically activated on TCK in JTAG mode.
64 RSTDVCC/SBWTDIO bidirectional Spy-Bi-Wire data input/output (SBWTDIO) for development tools and device programmers.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-64(9x9)
Category Embedded Processors & Controllers
Pins 65

CAD (KiCad official)

  • Symbol: MSP430F5247IRGCR
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: VQFN-64(9x9) (KiCad packages3D, STEP)
  • 3D model files: msp430f5247irgcr-etched.step / msp430f5247irgcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430f5247irgcr.step / msp430f5247irgcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (114 pp, sha256 9acee9f0b4b7514f, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF