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MSP430F5242IRGZR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430F5242IRGZR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-48-EP(7x7)
MSP430F5242IRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P6.3/A3/CB3 | bidirectional | General-purpose digital I/O that can also be ADC10 analog input A3 or Comparator_B input CB3; selecting CB3 disables the pin's output driver and input buffer. |
| 2 | P6.4/A4/CB4 | bidirectional | General-purpose digital I/O that can also be ADC10 analog input A4 or Comparator_B input CB4; selecting CB4 disables the pin's output driver and input buffer. |
| 3 | P6.5/A5/CB5 | bidirectional | General-purpose digital I/O that can also be ADC10 analog input A5 or Comparator_B input CB5; selecting CB5 disables the pin's output driver and input buffer. |
| 4 | P5.0/A8/VeREF+ | bidirectional | General-purpose digital I/O that can also be ADC10 analog input A8 or the external ADC reference input VeREF+; setting P5SEL.0 disables the output driver and input Schmitt trigger. |
| 5 | P5.1/A9/VeREF- | bidirectional | General-purpose digital I/O that can also be ADC10 analog input A9 or the negative external ADC reference terminal VeREF-; setting P5SEL.1 disables the output driver and input Schmitt trigger. |
| 6 | AVCC | power_in | Analog power supply for the device. |
| 7 | P5.4/XIN | bidirectional | General-purpose digital I/O; when XT1 crystal or bypass mode is selected it is the input terminal of crystal oscillator XT1. |
| 8 | P5.5/XOUT | bidirectional | General-purpose digital I/O; in XT1 crystal mode it is the output terminal of crystal oscillator XT1, and in bypass mode it can be used as general-purpose I/O. |
| 9 | AVSS | power_in | Analog ground supply. |
| 10 | DVCC | power_in | Digital power supply for the device. |
| 11 | DVSS | power_in | Digital ground supply. |
| 12 | VCORE | power_out | Regulated core power supply output for internal use only; no external current loading is possible and it should only be connected to the recommended capacitor CVCORE. |
| 13 | P1.0/TA0CLK/ACLK | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are the TA0CLK timer clock input and the ACLK output divided by 1, 2, 4, 8, 16, or 32. |
| 14 | P1.1/TA0.0 | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are TA0 CCR0 capture input CCI0A or compare output Out0, and the BSL transmit output. |
| 15 | P1.2/TA0.1 | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are TA0 CCR1 capture input CCI1A or compare output Out1, and the BSL receive input. |
| 16 | P1.3/TA0.2 | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are TA0 CCR2 capture input CCI2A or compare output Out2. |
| 17 | P1.4/TA0.3 | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are TA0 CCR3 capture input CCI3A or compare output Out3. |
| 18 | P1.5/TA0.4 | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are TA0 CCR4 capture input CCI4A or compare output Out4. |
| 19 | P1.6/TA1CLK/CBOUT | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are the TA1CLK timer clock input and the Comparator_B output CBOUT. |
| 20 | P1.7/TA1.0 | bidirectional | General-purpose digital I/O with port interrupt; alternate functions are TA1 CCR0 capture input CCI0A or compare output Out0. |
| 21 | P2.7/UCB0STE/UCA0CLK | bidirectional | General-purpose digital I/O; alternate function is the USCI_B0 SPI slave transmit enable or the USCI_A0 clock, with UCA0CLK taking precedence over UCB0STE. |
| 22 | P3.0/UCB0SIMO/UCB0SDA | bidirectional | General-purpose digital I/O; alternate functions are USCI_B0 SPI slave-in/master-out or I2C data (open drain, direction controlled by USCI). |
| 23 | P3.1/UCB0SOMI/UCB0SCL | bidirectional | General-purpose digital I/O; alternate functions are USCI_B0 SPI slave-out/master-in or I2C clock (open drain, direction controlled by USCI). |
| 24 | P3.2/UCB0CLK/UCA0STE | bidirectional | General-purpose digital I/O; alternate functions are the USCI_B0 clock input/output or the USCI_A0 SPI slave transmit enable, with UCB0CLK taking precedence over UCA0STE. |
| 25 | P3.3/UCA0TXD/UCA0SIMO | bidirectional | General-purpose digital I/O; alternate functions are USCI_A0 UART transmit (output) or USCI_A0 SPI slave-in/master-out. |
| 26 | P3.4/UCA0RXD/UCA0SOMI | bidirectional | General-purpose digital I/O; alternate functions are USCI_A0 UART receive (input) or USCI_A0 SPI slave-out/master-in. |
| 27 | P4.0/PM_UCB1STE/PM_UCA1CLK | bidirectional | General-purpose digital I/O whose default mapped secondary functions are USCI_B1 SPI slave transmit enable and USCI_A1 clock input/output, selectable through the port mapping controller. |
| 28 | P4.1/PM_UCB1SIMO/PM_UCB1SDA | bidirectional | General-purpose digital I/O whose default mapped secondary functions are USCI_B1 SPI slave-in/master-out and I2C data, selectable through the port mapping controller. |
| 29 | P4.2/PM_UCB1SOMI/PM_UCB1SCL | bidirectional | General-purpose digital I/O whose default mapped secondary functions are USCI_B1 SPI slave-out/master-in and I2C clock, selectable through the port mapping controller. |
| 30 | P4.3/PM_UCB1CLK/PM_UCA1STE | bidirectional | General-purpose digital I/O whose default mapped secondary functions are USCI_B1 clock input/output and USCI_A1 SPI slave transmit enable, selectable through the port mapping controller. |
| 31 | DVSS | power_in | Digital ground supply. |
| 32 | DVCC | power_in | Digital power supply for the device. |
| 33 | P4.4/PM_UCA1TXD/PM_UCA1SIMO | bidirectional | General-purpose digital I/O whose default mapped secondary functions are USCI_A1 UART transmit (output) or USCI_A1 SPI slave-in/master-out, selectable through the port mapping controller. |
| 34 | P4.5/PM_UCA1RXD/PM_UCA1SOMI | bidirectional | General-purpose digital I/O whose default mapped secondary functions are USCI_A1 UART receive (input) or USCI_A1 SPI slave-out/master-in, selectable through the port mapping controller. |
| 35 | P4.6/PM_NONE | bidirectional | General-purpose digital I/O; its default port mapping is PM_NONE, which connects no secondary function and routes the output to DVSS. |
| 36 | NC | unconnected | Not connected. |
| 37 | RST/NMI | input | Reset / non-maskable interrupt pin, listed with the Schmitt-trigger inputs in Section 5.7; its detailed function text is not in the supplied pages. |
| 38 | P5.2/XT2IN | bidirectional | General-purpose digital I/O; when XT2 crystal or bypass mode is selected it is the XT2IN input of the high-frequency crystal oscillator. |
| 39 | P5.3/XT2OUT | bidirectional | General-purpose digital I/O; in XT2 crystal mode it is the XT2OUT output, and in bypass mode it can be used as general-purpose I/O. |
| 40 | TEST/SBWTCK | input | Test-mode pin that serves as the Spy-Bi-Wire clock input (SBWTCK) for development tools and device programmers. |
| 41 | PJ.0/TDO | bidirectional | JTAG pin TDO, which is also a general-purpose I/O (PJ.0) with Schmitt trigger or output function; direction is controlled by the JTAG module. |
| 42 | PJ.1/TDI/TCLK | bidirectional | JTAG pin TDI/TCLK, also a general-purpose I/O (PJ.1) with Schmitt trigger or output function; pullups are automatically activated in JTAG mode. |
| 43 | PJ.2/TMS | bidirectional | JTAG pin TMS, also a general-purpose I/O (PJ.2) with Schmitt trigger or output function; pullups are automatically activated in JTAG mode. |
| 44 | PJ.3/TCK | bidirectional | JTAG pin TCK, also a general-purpose I/O (PJ.3) with Schmitt trigger or output function; pullups are automatically activated in JTAG mode. |
| 45 | RSTDVCC/SBWTDIO | bidirectional | Spy-Bi-Wire data input/output (SBWTDIO) pin, listed with the Schmitt-trigger inputs in Section 5.7; the RSTDVCC function detail is not in the supplied pages. |
| 46 | P6.0/A0/CB0 | bidirectional | General-purpose digital I/O that can also be ADC10 analog input A0 or Comparator_B input CB0; selecting CB0 disables the pin's output driver and input buffer. |
| 47 | P6.1/A1/CB1 | bidirectional | General-purpose digital I/O that can also be ADC10 analog input A1 or Comparator_B input CB1; selecting CB1 disables the pin's output driver and input buffer. |
| 48 | P6.2/A2/CB2 | bidirectional | General-purpose digital I/O that can also be ADC10 analog input A2 or Comparator_B input CB2; selecting CB2 disables the pin's output driver and input buffer. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
MSP430F5242IRGZR - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
msp430f5242irgzr-etched.step/msp430f5242irgzr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430f5242irgzr.step/msp430f5242irgzr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (114 pp, sha256
9acee9f0b4b7514f, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).