component
MSP430F5234IRGZR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MSP430F5234IRGZR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-48-EP(7x7)
MSP430F5234IRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P6.3/CB3 | bidirectional | General-purpose digital I/O with Comparator_B input CB3; setting CBPD.3 disables the output driver and Schmitt trigger to prevent parasitic cross currents on analog signals. |
| 2 | P6.4/CB4 | bidirectional | General-purpose digital I/O with Comparator_B input CB4, and analog input A4 for the ADC where that device type provides it. |
| 3 | P6.5/CB5 | bidirectional | General-purpose digital I/O with Comparator_B input CB5, and analog input A5 for the ADC where that device type provides it. |
| 4 | P5.0 | bidirectional | General-purpose digital I/O; the ADC analog input A8 and VeREF+ external reference function are listed as not available on all device types. |
| 5 | P5.1 | bidirectional | General-purpose digital I/O; the ADC analog input A9 and VeREF- external reference function are listed as not available on all device types. |
| 6 | AVCC | power_in | Analog power supply. |
| 7 | P5.4/XIN | bidirectional | General-purpose digital I/O; input terminal for crystal oscillator XT1 when the port function is selected. |
| 8 | P5.5/XOUT | bidirectional | General-purpose digital I/O; output terminal of crystal oscillator XT1 in crystal mode, and general-purpose I/O when XT1 is used in bypass mode. |
| 9 | AVSS | power_in | Analog ground supply. |
| 10 | DVCC | power_in | Digital power supply. |
| 11 | DVSS | power_in | Digital ground supply. |
| 12 | VCORE | power_out | Regulated core power supply output for internal use only; no external current loading is possible and only the recommended capacitor CVCORE should be connected. |
| 13 | P1.0/TA0CLK/ACLK | bidirectional | General-purpose digital I/O with port interrupt; TA0CLK timer clock input or ACLK output divided by 1, 2, 4, 8, 16, or 32. |
| 14 | P1.1/TA0.0 | bidirectional | General-purpose digital I/O with port interrupt; TA0 CCR0 capture input CCI0A or compare output Out0, and BSL transmit output. |
| 15 | P1.2/TA0.1 | bidirectional | General-purpose digital I/O with port interrupt; TA0 CCR1 capture input CCI1A or compare output Out1, and BSL receive input. |
| 16 | P1.3/TA0.2 | bidirectional | General-purpose digital I/O with port interrupt; TA0 CCR2 capture input CCI2A or compare output Out2. |
| 17 | P1.4/TA0.3 | bidirectional | General-purpose digital I/O; TA0.CCI3A capture input or TA0.3 output. |
| 18 | P1.5/TA0.4 | bidirectional | General-purpose digital I/O; TA0.CCI4A capture input or TA0.4 output. |
| 19 | P1.6/TA1CLK/CBOUT | bidirectional | General-purpose digital I/O; TA1CLK timer clock input or Comparator_B output CBOUT. |
| 20 | P1.7/TA1.0 | bidirectional | General-purpose digital I/O; TA1.CCI0A capture input or TA1.0 output. |
| 21 | P2.7/UCB0STE/UCA0CLK | bidirectional | General-purpose digital I/O; UCB0STE or UCA0CLK function with direction controlled by the USCI, where UCA0CLK takes precedence over UCB0STE. |
| 22 | P3.0/UCB0SIMO/UCB0SDA | bidirectional | General-purpose digital I/O; USCI_B0 SPI SIMO or I2C SDA function, where in I2C mode the output drives only logic 0 to VSS. |
| 23 | P3.1/UCB0SOMI/UCB0SCL | bidirectional | General-purpose digital I/O; USCI_B0 SPI SOMI or I2C SCL function, where in I2C mode the output drives only logic 0 to VSS. |
| 24 | P3.2/UCB0CLK/UCA0STE | bidirectional | General-purpose digital I/O; USCI_B0 clock or USCI_A0 SPI STE function, where UCB0CLK takes precedence over UCA0STE. |
| 25 | P3.3/UCA0TXD/UCA0SIMO | bidirectional | General-purpose digital I/O; USCI_A0 UART TXD or SPI SIMO function. |
| 26 | P3.4/UCA0RXD/UCA0SOMI | bidirectional | General-purpose digital I/O; USCI_A0 UART RXD or SPI SOMI function. |
| 27 | P4.0/PM_UCB1STE/PM_UCA1CLK | bidirectional | General-purpose digital I/O; port-mapped secondary function (default mapping USCI_B1 SPI STE or USCI_A1 clock), with direction controlled by the USCI. |
| 28 | P4.1/PM_UCB1SIMO/PM_UCB1SDA | bidirectional | General-purpose digital I/O; port-mapped USCI_B1 SPI SIMO or I2C SDA function (open drain for I2C). |
| 29 | P4.2/PM_UCB1SOMI/PM_UCB1SCL | bidirectional | General-purpose digital I/O; port-mapped USCI_B1 SPI SOMI or I2C SCL function (open drain for I2C). |
| 30 | P4.3/PM_UCB1CLK/PM_UCA1STE | bidirectional | General-purpose digital I/O; port-mapped USCI_B1 clock or USCI_A1 SPI STE function. |
| 31 | DVSS | power_in | Digital ground supply. |
| 32 | DVCC | power_in | Digital power supply. |
| 33 | P4.4/PM_UCA1TXD/PM_UCA1SIMO | bidirectional | General-purpose digital I/O; port-mapped USCI_A1 UART TXD or SPI SIMO function. |
| 34 | P4.5/PM_UCA1RXD/PM_UCA1SOMI | bidirectional | General-purpose digital I/O; port-mapped USCI_A1 UART RXD or SPI SOMI function. |
| 35 | P4.6/PM_NONE | bidirectional | General-purpose digital I/O; default port mapping PM_NONE connects no peripheral function (input to DVSS). |
| 36 | NC | unconnected | Not connected; the provided pages give no further electrical function for this terminal. |
| 37 | RST/NMI | input | Reset / non-maskable interrupt terminal, listed among the Schmitt-trigger inputs in Section 5.7 of the datasheet. |
| 38 | P5.2/XT2IN | bidirectional | General-purpose digital I/O; XT2IN input of the high-frequency crystal oscillator XT2 when P5SEL.2 is set, in crystal or bypass mode per XT2BYPASS. |
| 39 | P5.3/XT2OUT | bidirectional | General-purpose digital I/O; XT2OUT output of crystal oscillator XT2 in crystal mode, and general-purpose I/O when XT2 is in bypass mode. |
| 40 | TEST/SBWTCK | input | Spy-Bi-Wire clock input for device programming and debug. |
| 41 | PJ.0/TDO | bidirectional | JTAG TDO output, which is also usable as general-purpose I/O with Schmitt trigger input or output when JTAG is not using it. |
| 42 | PJ.1/TDI/TCLK | bidirectional | JTAG TDI/TCLK input with direction controlled by the JTAG module; pullups are activated automatically in JTAG mode. |
| 43 | PJ.2/TMS | bidirectional | JTAG TMS input with direction controlled by the JTAG module; pullups are activated automatically in JTAG mode. |
| 44 | PJ.3/TCK | bidirectional | JTAG TCK input with direction controlled by the JTAG module; pullups are activated automatically in JTAG mode. |
| 45 | RSTDVCC/SBWTDIO | bidirectional | Spy-Bi-Wire data input/output (SBWTDIO), also listed among the Schmitt-trigger inputs in Section 5.7. |
| 46 | P6.0/CB0 | bidirectional | General-purpose digital I/O with Comparator_B input CB0; setting CBPD.0 disables the output driver and Schmitt trigger for analog signals. |
| 47 | P6.1/CB1 | bidirectional | General-purpose digital I/O with Comparator_B input CB1; setting CBPD.1 disables the output driver and Schmitt trigger for analog signals. |
| 48 | P6.2/CB2 | bidirectional | General-purpose digital I/O with Comparator_B input CB2; setting CBPD.2 disables the output driver and Schmitt trigger for analog signals. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
MSP430F5234IRGZR - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
msp430f5234irgzr-etched.step/msp430f5234irgzr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430f5234irgzr.step/msp430f5234irgzr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (114 pp, sha256
9acee9f0b4b7514f, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MSP430F5234IRGZR
**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · VQFN-48-EP(7x7)
MSP430F5234IRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P6.3/CB3 | bidirectional | General-purpose digital I/O with Comparator_B input CB3; setting CBPD.3 disables the output driver and Schmitt trigger to prevent parasitic cross currents on analog signals. |
| 2 | P6.4/CB4 | bidirectional | General-purpose digital I/O with Comparator_B input CB4, and analog input A4 for the ADC where that device type provides it. |
| 3 | P6.5/CB5 | bidirectional | General-purpose digital I/O with Comparator_B input CB5, and analog input A5 for the ADC where that device type provides it. |
| 4 | P5.0 | bidirectional | General-purpose digital I/O; the ADC analog input A8 and VeREF+ external reference function are listed as not available on all device types. |
| 5 | P5.1 | bidirectional | General-purpose digital I/O; the ADC analog input A9 and VeREF- external reference function are listed as not available on all device types. |
| 6 | AVCC | power_in | Analog power supply. |
| 7 | P5.4/XIN | bidirectional | General-purpose digital I/O; input terminal for crystal oscillator XT1 when the port function is selected. |
| 8 | P5.5/XOUT | bidirectional | General-purpose digital I/O; output terminal of crystal oscillator XT1 in crystal mode, and general-purpose I/O when XT1 is used in bypass mode. |
| 9 | AVSS | power_in | Analog ground supply. |
| 10 | DVCC | power_in | Digital power supply. |
| 11 | DVSS | power_in | Digital ground supply. |
| 12 | VCORE | power_out | Regulated core power supply output for internal use only; no external current loading is possible and only the recommended capacitor CVCORE should be connected. |
| 13 | P1.0/TA0CLK/ACLK | bidirectional | General-purpose digital I/O with port interrupt; TA0CLK timer clock input or ACLK output divided by 1, 2, 4, 8, 16, or 32. |
| 14 | P1.1/TA0.0 | bidirectional | General-purpose digital I/O with port interrupt; TA0 CCR0 capture input CCI0A or compare output Out0, and BSL transmit output. |
| 15 | P1.2/TA0.1 | bidirectional | General-purpose digital I/O with port interrupt; TA0 CCR1 capture input CCI1A or compare output Out1, and BSL receive input. |
| 16 | P1.3/TA0.2 | bidirectional | General-purpose digital I/O with port interrupt; TA0 CCR2 capture input CCI2A or compare output Out2. |
| 17 | P1.4/TA0.3 | bidirectional | General-purpose digital I/O; TA0.CCI3A capture input or TA0.3 output. |
| 18 | P1.5/TA0.4 | bidirectional | General-purpose digital I/O; TA0.CCI4A capture input or TA0.4 output. |
| 19 | P1.6/TA1CLK/CBOUT | bidirectional | General-purpose digital I/O; TA1CLK timer clock input or Comparator_B output CBOUT. |
| 20 | P1.7/TA1.0 | bidirectional | General-purpose digital I/O; TA1.CCI0A capture input or TA1.0 output. |
| 21 | P2.7/UCB0STE/UCA0CLK | bidirectional | General-purpose digital I/O; UCB0STE or UCA0CLK function with direction controlled by the USCI, where UCA0CLK takes precedence over UCB0STE. |
| 22 | P3.0/UCB0SIMO/UCB0SDA | bidirectional | General-purpose digital I/O; USCI_B0 SPI SIMO or I2C SDA function, where in I2C mode the output drives only logic 0 to VSS. |
| 23 | P3.1/UCB0SOMI/UCB0SCL | bidirectional | General-purpose digital I/O; USCI_B0 SPI SOMI or I2C SCL function, where in I2C mode the output drives only logic 0 to VSS. |
| 24 | P3.2/UCB0CLK/UCA0STE | bidirectional | General-purpose digital I/O; USCI_B0 clock or USCI_A0 SPI STE function, where UCB0CLK takes precedence over UCA0STE. |
| 25 | P3.3/UCA0TXD/UCA0SIMO | bidirectional | General-purpose digital I/O; USCI_A0 UART TXD or SPI SIMO function. |
| 26 | P3.4/UCA0RXD/UCA0SOMI | bidirectional | General-purpose digital I/O; USCI_A0 UART RXD or SPI SOMI function. |
| 27 | P4.0/PM_UCB1STE/PM_UCA1CLK | bidirectional | General-purpose digital I/O; port-mapped secondary function (default mapping USCI_B1 SPI STE or USCI_A1 clock), with direction controlled by the USCI. |
| 28 | P4.1/PM_UCB1SIMO/PM_UCB1SDA | bidirectional | General-purpose digital I/O; port-mapped USCI_B1 SPI SIMO or I2C SDA function (open drain for I2C). |
| 29 | P4.2/PM_UCB1SOMI/PM_UCB1SCL | bidirectional | General-purpose digital I/O; port-mapped USCI_B1 SPI SOMI or I2C SCL function (open drain for I2C). |
| 30 | P4.3/PM_UCB1CLK/PM_UCA1STE | bidirectional | General-purpose digital I/O; port-mapped USCI_B1 clock or USCI_A1 SPI STE function. |
| 31 | DVSS | power_in | Digital ground supply. |
| 32 | DVCC | power_in | Digital power supply. |
| 33 | P4.4/PM_UCA1TXD/PM_UCA1SIMO | bidirectional | General-purpose digital I/O; port-mapped USCI_A1 UART TXD or SPI SIMO function. |
| 34 | P4.5/PM_UCA1RXD/PM_UCA1SOMI | bidirectional | General-purpose digital I/O; port-mapped USCI_A1 UART RXD or SPI SOMI function. |
| 35 | P4.6/PM_NONE | bidirectional | General-purpose digital I/O; default port mapping PM_NONE connects no peripheral function (input to DVSS). |
| 36 | NC | unconnected | Not connected; the provided pages give no further electrical function for this terminal. |
| 37 | RST/NMI | input | Reset / non-maskable interrupt terminal, listed among the Schmitt-trigger inputs in Section 5.7 of the datasheet. |
| 38 | P5.2/XT2IN | bidirectional | General-purpose digital I/O; XT2IN input of the high-frequency crystal oscillator XT2 when P5SEL.2 is set, in crystal or bypass mode per XT2BYPASS. |
| 39 | P5.3/XT2OUT | bidirectional | General-purpose digital I/O; XT2OUT output of crystal oscillator XT2 in crystal mode, and general-purpose I/O when XT2 is in bypass mode. |
| 40 | TEST/SBWTCK | input | Spy-Bi-Wire clock input for device programming and debug. |
| 41 | PJ.0/TDO | bidirectional | JTAG TDO output, which is also usable as general-purpose I/O with Schmitt trigger input or output when JTAG is not using it. |
| 42 | PJ.1/TDI/TCLK | bidirectional | JTAG TDI/TCLK input with direction controlled by the JTAG module; pullups are activated automatically in JTAG mode. |
| 43 | PJ.2/TMS | bidirectional | JTAG TMS input with direction controlled by the JTAG module; pullups are activated automatically in JTAG mode. |
| 44 | PJ.3/TCK | bidirectional | JTAG TCK input with direction controlled by the JTAG module; pullups are activated automatically in JTAG mode. |
| 45 | RSTDVCC/SBWTDIO | bidirectional | Spy-Bi-Wire data input/output (SBWTDIO), also listed among the Schmitt-trigger inputs in Section 5.7. |
| 46 | P6.0/CB0 | bidirectional | General-purpose digital I/O with Comparator_B input CB0; setting CBPD.0 disables the output driver and Schmitt trigger for analog signals. |
| 47 | P6.1/CB1 | bidirectional | General-purpose digital I/O with Comparator_B input CB1; setting CBPD.1 disables the output driver and Schmitt trigger for analog signals. |
| 48 | P6.2/CB2 | bidirectional | General-purpose digital I/O with Comparator_B input CB2; setting CBPD.2 disables the output driver and Schmitt trigger for analog signals. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
## CAD (KiCad official)
- Symbol: `MSP430F5234IRGZR`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files: `msp430f5234irgzr-etched.step` / `msp430f5234irgzr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430f5234irgzr.step` / `msp430f5234irgzr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430f5239) (114 pp, sha256 `9acee9f0b4b7514f`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/msp430f5234irgzr-datasheet.pdf)