component
MSP430F479IPNR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430F479IPNR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)
MSP430F479IPNR from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DVCC1 | power_in | Digital supply voltage, positive terminal; supplies all digital parts. |
| 2 | P2.2/TB1 | bidirectional | General-purpose digital I/O pin; Timer_B capture CCI1A/B input and compare Out1 output. |
| 3 | P2.1/TB0/S0 | bidirectional | General-purpose digital I/O pin; Timer_B capture CCI0A/B input and compare Out0 output, also LCD segment output 0. |
| 4 | P2.0/TA2/S1 | bidirectional | General-purpose digital I/O pin; Timer_A capture CCI2A/B input and compare Out2 output, also LCD segment output 1. |
| 5 | P2.6/CAOUT/S2 | bidirectional | General-purpose digital I/O pin; Comparator_A output, also LCD segment output 2. |
| 6 | P2.7/S3 | bidirectional | General-purpose digital I/O pin; also LCD segment output 3. |
| 7 | GND | power_in | Ground used to shield the oscillator; it is recommended to connect GND externally to DVSS. |
| 8 | XIN | input | Input port for crystal oscillator XT1; standard or watch crystals can be connected. |
| 9 | XOUT | output | Output port for crystal oscillator XT1; standard or watch crystals can be connected. |
| 10 | GND | power_in | Ground used to shield the oscillator; it is recommended to connect GND externally to DVSS. |
| 11 | P4.7/S4 | bidirectional | General-purpose digital I/O pin; also LCD segment output 4. |
| 12 | P4.6/S5 | bidirectional | General-purpose digital I/O pin; also LCD segment output 5. |
| 13 | P4.5/S6 | bidirectional | General-purpose digital I/O pin; also LCD segment output 6. |
| 14 | P4.4/S7 | bidirectional | General-purpose digital I/O pin; also LCD segment output 7. |
| 15 | P4.3/S8 | bidirectional | General-purpose digital I/O pin; also LCD segment output 8. |
| 16 | P4.2/S9 | bidirectional | General-purpose digital I/O pin; also LCD segment output 9. |
| 17 | P4.1/S10 | bidirectional | General-purpose digital I/O pin; also LCD segment output 10. |
| 18 | P4.0/S11 | bidirectional | General-purpose digital I/O pin; also LCD segment output 11. |
| 19 | S12 | output | LCD segment output 12. |
| 20 | S13 | output | LCD segment output 13. |
| 21 | S14 | output | LCD segment output 14. |
| 22 | S15 | output | LCD segment output 15. |
| 23 | S16 | output | LCD segment output 16. |
| 24 | S17 | output | LCD segment output 17. |
| 25 | S18 | output | LCD segment output 18. |
| 26 | S19 | output | LCD segment output 19. |
| 27 | P5.0/S20 | bidirectional | General-purpose digital I/O pin; also LCD segment output 20. |
| 28 | P5.1/S21 | bidirectional | General-purpose digital I/O pin; also LCD segment output 21. |
| 29 | S22 | output | LCD segment output 22. |
| 30 | S23 | output | LCD segment output 23. |
| 31 | S24 | output | LCD segment output 24. |
| 32 | S25 | output | LCD segment output 25. |
| 33 | COM0 | output | Common output; COM0-3 are used for LCD backplanes. |
| 34 | P5.2/COM1 | bidirectional | General-purpose digital I/O pin; also LCD common output COM1. |
| 35 | P5.3/COM2 | bidirectional | General-purpose digital I/O pin; also LCD common output COM2. |
| 36 | P5.4/COM3 | bidirectional | General-purpose digital I/O pin; also LCD common output COM3. |
| 37 | LCDCAP/R33 | bidirectional | Capacitor connection for the LCD charge pump and input port of the most positive analog LCD level (V4). |
| 38 | P5.5/R23 | bidirectional | General-purpose digital I/O pin; input port of the second most positive analog LCD level (V3). |
| 39 | P5.6/LCDREF/R13 | bidirectional | General-purpose digital I/O pin; external LCD reference voltage input and input port of the third most positive analog LCD level. |
| 40 | P5.7/R03 | bidirectional | General-purpose digital I/O pin; input port of the fourth most positive analog LCD level (V1). |
| 41 | P3.0/UCB0STE/UCA0CLK | bidirectional | General-purpose digital I/O pin; USCI_B0 slave transmit enable and USCI_A0 clock input/output. |
| 42 | P3.1/UCB0SIMO/UCB0SDA/S26 | bidirectional | General-purpose digital I/O pin; USCI_B0 slave in/master out in SPI mode, SDA I2C data in I2C mode, also LCD segment output 26. |
| 43 | P3.2/UCB0SOMI/UCB0SCL/S27 | bidirectional | General-purpose digital I/O pin; USCI_B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode, also LCD segment output 27. |
| 44 | P3.3/UCB0CLK/UCA0STE | bidirectional | General-purpose digital I/O pin; USCI_B0 clock input/output and USCI_A0 slave transmit enable. |
| 45 | P3.4/S28 | bidirectional | General-purpose digital I/O pin; also LCD segment output 28. |
| 46 | P3.5/S29 | bidirectional | General-purpose digital I/O pin; also LCD segment output 29. |
| 47 | P3.6/S30 | bidirectional | General-purpose digital I/O pin; also LCD segment output 30. |
| 48 | P3.7/S31 | bidirectional | General-purpose digital I/O pin; also LCD segment output 31. |
| 49 | P1.7/CA1/A2+ | bidirectional | General-purpose digital I/O pin; Comparator_A input 1 and SD16 positive analog input A2. |
| 50 | P1.6/CA0/A2-/DAC0 | bidirectional | General-purpose digital I/O pin; Comparator_A input 0, SD16 negative analog input A2, and DAC12.0 output. |
| 51 | P1.5/TACLK/ACLK/A3+ | bidirectional | General-purpose digital I/O pin; Timer_A clock input TACLK, ACLK signal output, and SD16 positive analog input A3. |
| 52 | AVCC | power_in | Analog supply voltage, positive terminal. |
| 53 | AVSS | power_in | Analog supply voltage, negative terminal. |
| 54 | P1.4/TBCLK/SMCLK/A3- | bidirectional | General-purpose digital I/O pin; Timer_B clock input TBCLK, SMCLK signal output, and SD16 negative analog input A3. |
| 55 | P1.3/TBOUTH/SVSOUT/A4+ | bidirectional | General-purpose digital I/O pin; Timer_B TB0-TB2 PWM output high-impedance control (TBOUTH), SVS comparator output, and SD16 positive analog input A4. |
| 56 | P1.2/TA1/A4- | bidirectional | General-purpose digital I/O pin; Timer_A capture CCI1A input, compare Out1 output, and SD16 negative analog input A4. |
| 57 | P1.1/TA0/MCLK | bidirectional | General-purpose digital I/O pin; Timer_A capture CCI0B input, compare Out0 output, MCLK signal output, and BSL receive. |
| 58 | P1.0/TA0 | bidirectional | General-purpose digital I/O pin; Timer_A capture CCI0A input, compare Out0 output, and BSL transmit. |
| 59 | P6.7/SVSIN | bidirectional | General-purpose digital I/O pin; SVS input. |
| 60 | VREF | power_in | Input for an external reference voltage or internal reference voltage output. |
| 61 | P6.6 | bidirectional | General-purpose digital I/O pin. |
| 62 | P6.5 | bidirectional | General-purpose digital I/O pin. |
| 63 | P6.4/A1- | bidirectional | General-purpose digital I/O pin; SD16 negative analog input A1. |
| 64 | P6.3/A1+ | bidirectional | General-purpose digital I/O pin; SD16 positive analog input A1. |
| 65 | P6.2 | bidirectional | General-purpose digital I/O pin. |
| 66 | P6.1/A0- | bidirectional | General-purpose digital I/O pin; SD16 negative analog input A0. |
| 67 | P6.0/A0+ | bidirectional | General-purpose digital I/O pin; SD16 positive analog input A0. |
| 68 | XT2OUT | output | Output terminal of crystal oscillator XT2. |
| 69 | XT2IN | input | Input port for crystal oscillator XT2. |
| 70 | TDO/TDI | bidirectional | Test data output port; TDO/TDI data output or programming data input terminal. |
| 71 | TDI/TCLK | input | Test data input or test clock input; the device protection fuse is connected to this pin. |
| 72 | TMS | input | Test mode select; used as an input port for device programming and test. |
| 73 | TCK | input | Test clock (JTAG); clock input for device programming, test, and bootloader start. |
| 74 | RST/NMI | input | Reset input, nonmaskable interrupt input port, or bootloader start (in flash devices). |
| 75 | P2.5/UCA0RXD/UCA0SOMI | bidirectional | General-purpose digital I/O pin; USCI_A0 receive data input in UART mode and slave data out/master in in SPI mode. |
| 76 | P2.4/UCA0TXD/UCA0SIMO | bidirectional | General-purpose digital I/O pin; USCI_A0 transmit data output in UART mode and slave data in/master out in SPI mode. |
| 77 | P2.3/TB2 | bidirectional | General-purpose digital I/O pin; Timer_B capture CCI2A/B input and compare Out2 output. |
| 78 | DVSS2 | power_in | Digital supply voltage, negative terminal; supplies all digital parts. |
| 79 | DVSS1 | power_in | Digital supply voltage, negative terminal; supplies all digital parts. |
| 80 | DVCC2 | power_in | Digital supply voltage, positive terminal; supplies all digital parts. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-80(12x12) |
| Category | Embedded Processors & Controllers |
| Pins | 80 |
CAD (KiCad official)
- Symbol:
MSP430F479IPNR - Footprint:
Package_QFP:LQFP-80_12x12mm_P0.5mm - 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
- 3D model files:
msp430f479ipnr-etched.step/msp430f479ipnr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430f479ipnr.step/msp430f479ipnr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (98 pp, sha256
122cc53024d516f1, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).