component
MSP430F4794IPZR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), QFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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MSP430F4794IPZR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · QFP-100(14x14)
MSP430F4794IPZR from Texas Instruments, in a QFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DVCC1 | power_in | Digital supply voltage, positive terminal. |
| 2 | A0.0+ | input | SD16_A positive analog input A0.0; leave open if unused. |
| 3 | A0.0− | input | SD16_A negative analog input A0.0; leave open if unused. |
| 4 | A1.0+ | input | SD16_A positive analog input A1.0; leave open if unused. |
| 5 | A1.0− | input | SD16_A negative analog input A1.0; leave open if unused. |
| 6 | A2.0+ | input | SD16_A positive analog input A2.0; leave open if unused. |
| 7 | A2.0− | input | SD16_A negative analog input A2.0; leave open if unused. |
| 8 | XIN | input | Input port for crystal oscillator XT1; standard or watch crystals can be connected. |
| 9 | XOUT | output | Output terminal of crystal oscillator XT1. |
| 10 | VREF | power_in | Input for an external reference voltage or internal reference voltage output, which can be used as mid-voltage. |
| 11 | NC | unconnected | Internally not connected; can be connected to VSS. |
| 12 | P5.1/S0 | bidirectional | General-purpose digital I/O with LCD segment output S0. |
| 13 | S1 | output | LCD segment output S1. |
| 14 | P10.7/S2 | bidirectional | General-purpose digital I/O with LCD segment output S2. |
| 15 | P10.6/S3 | bidirectional | General-purpose digital I/O with LCD segment output S3. |
| 16 | P10.5/S4 | bidirectional | General-purpose digital I/O with LCD segment output S4. |
| 17 | P10.4/S5 | bidirectional | General-purpose digital I/O with LCD segment output S5. |
| 18 | P10.3/S6 | bidirectional | General-purpose digital I/O with LCD segment output S6. |
| 19 | P10.2/S7 | bidirectional | General-purpose digital I/O with LCD segment output S7. |
| 20 | P10.1/S8 | bidirectional | General-purpose digital I/O with LCD segment output S8. |
| 21 | P10.0/S9 | bidirectional | General-purpose digital I/O with LCD segment output S9. |
| 22 | P9.7/S10 | bidirectional | General-purpose digital I/O with LCD segment output S10. |
| 23 | P9.6/S11 | bidirectional | General-purpose digital I/O with LCD segment output S11. |
| 24 | P9.5/S12 | bidirectional | General-purpose digital I/O with LCD segment output S12. |
| 25 | P9.4/S13 | bidirectional | General-purpose digital I/O with LCD segment output S13. |
| 26 | P9.3/S14 | bidirectional | General-purpose digital I/O with LCD segment output S14. |
| 27 | P9.2/S15 | bidirectional | General-purpose digital I/O with LCD segment output S15. |
| 28 | P9.1/S16 | bidirectional | General-purpose digital I/O with LCD segment output S16. |
| 29 | P9.0/S17 | bidirectional | General-purpose digital I/O with LCD segment output S17. |
| 30 | P8.7/S18 | bidirectional | General-purpose digital I/O with LCD segment output S18. |
| 31 | P8.6/S19 | bidirectional | General-purpose digital I/O with LCD segment output S19. |
| 32 | P8.5/S20 | bidirectional | General-purpose digital I/O with LCD segment output S20. |
| 33 | P8.4/S21 | bidirectional | General-purpose digital I/O with LCD segment output S21. |
| 34 | P8.3/S22 | bidirectional | General-purpose digital I/O with LCD segment output S22. |
| 35 | P8.2/S23 | bidirectional | General-purpose digital I/O with LCD segment output S23. |
| 36 | P8.1/S24 | bidirectional | General-purpose digital I/O with LCD segment output S24. |
| 37 | P8.0/S25 | bidirectional | General-purpose digital I/O with LCD segment output S25. |
| 38 | P7.7/S26 | bidirectional | General-purpose digital I/O with LCD segment output S26. |
| 39 | P7.6/S27 | bidirectional | General-purpose digital I/O with LCD segment output S27. |
| 40 | P7.5/S28 | bidirectional | General-purpose digital I/O with LCD segment output S28. |
| 41 | P7.4/S29 | bidirectional | General-purpose digital I/O with LCD segment output S29. |
| 42 | P7.3/S30 | bidirectional | General-purpose digital I/O with LCD segment output S30. |
| 43 | P7.2/S31 | bidirectional | General-purpose digital I/O with LCD segment output S31. |
| 44 | P7.1/S32 | bidirectional | General-purpose digital I/O with LCD segment output S32. |
| 45 | P7.0/S33 | bidirectional | General-purpose digital I/O with LCD segment output S33. |
| 46 | P4.7/S34 | bidirectional | General-purpose digital I/O with LCD segment output S34. |
| 47 | P4.6/S35 | bidirectional | General-purpose digital I/O with LCD segment output S35. |
| 48 | P4.5/UCB1CLK/UCA1STE/S36 | bidirectional | General-purpose digital I/O; USCI_B1 clock input/output or USCI_A1 slave transmit enable; LCD segment output S36. |
| 49 | P4.4/UCB1SOMI/UCB1SCL/S37 | bidirectional | General-purpose digital I/O; USCI_B1 SOMI in SPI mode or SCL in I2C mode; LCD segment output S37. In I2C mode the output drives only logic 0 to VSS. |
| 50 | P4.3/UCB1SIMO/UCB1SDA/S38 | bidirectional | General-purpose digital I/O; USCI_B1 SIMO in SPI mode or SDA in I2C mode; LCD segment output S38. In I2C mode the output drives only logic 0 to VSS. |
| 51 | P4.2/UCB1STE/UCA1CLK/S39 | bidirectional | General-purpose digital I/O; USCI_B1 slave transmit enable or USCI_A1 clock input/output; LCD segment output S39. |
| 52 | COM0 | output | LCD backplane common output COM0. |
| 53 | P5.2/COM1 | bidirectional | General-purpose digital I/O or LCD backplane common output COM1. |
| 54 | P5.3/COM2 | bidirectional | General-purpose digital I/O or LCD backplane common output COM2. |
| 55 | P5.4/COM3 | bidirectional | General-purpose digital I/O or LCD backplane common output COM3. |
| 56 | P5.5/R03 | bidirectional | General-purpose digital I/O; input port of the lowest analog LCD level V5. |
| 57 | P5.6/LCDREF/R13 | bidirectional | General-purpose digital I/O; external reference voltage input for regulated LCD voltage or input port of third most positive analog LCD level (V4 or V3). |
| 58 | P5.7/R23 | bidirectional | General-purpose digital I/O; input port of second most positive analog LCD level V2. |
| 59 | LCDCAP/R33 | input | LCD capacitor connection; input/output port of the most positive analog LCD level V1. |
| 60 | DVCC2 | power_in | Digital supply voltage, positive terminal. |
| 61 | DVSS2 | power_in | Digital supply voltage, negative terminal (ground). |
| 62 | P4.1/UCA1RXD/UCA1SOMI | bidirectional | General-purpose digital I/O; USCI_A1 receive data input in UART mode or slave out/master in in SPI mode. |
| 63 | P4.0/UCA1TXD/UCA1SIMO | bidirectional | General-purpose digital I/O; USCI_A1 transmit data output in UART mode or slave in/master out in SPI mode. |
| 64 | P3.7 | bidirectional | General-purpose digital I/O with pull-up/pull-down resistor capability. |
| 65 | P3.6 | bidirectional | General-purpose digital I/O with pull-up/pull-down resistor capability. |
| 66 | P3.5 | bidirectional | General-purpose digital I/O with pull-up/pull-down resistor capability. |
| 67 | P3.4 | bidirectional | General-purpose digital I/O with pull-up/pull-down resistor capability. |
| 68 | P3.3/UCB0CLK/UCA0STE | bidirectional | General-purpose digital I/O; USCI_B0 clock input/output or USCI_A0 slave transmit enable. |
| 69 | P3.2/UCB0SOMI/UCB0SCL | bidirectional | General-purpose digital I/O; USCI_B0 SOMI in SPI mode or SCL in I2C mode. |
| 70 | P3.1/UCB0SIMO/UCB0SDA | bidirectional | General-purpose digital I/O; USCI_B0 SIMO in SPI mode or SDA in I2C mode. |
| 71 | P3.0/UCB0STE/UCA0CLK | bidirectional | General-purpose digital I/O; USCI_B0 slave transmit enable or USCI_A0 clock input/output. |
| 72 | P2.7 | bidirectional | General-purpose digital I/O. |
| 73 | P2.6/CAOUT | bidirectional | General-purpose digital I/O or Comparator_A output. |
| 74 | P2.5/UCA0RXD/UCA0SOMI | bidirectional | General-purpose digital I/O; USCI_A0 receive data input in UART mode or slave out/master in in SPI mode. |
| 75 | P2.4/UCA0TXD/UCA0SIMO | bidirectional | General-purpose digital I/O; USCI_A0 transmit data output in UART mode or slave in/master out in SPI mode. |
| 76 | P2.3/TB2 | bidirectional | General-purpose digital I/O; Timer_B CCR2 capture input (CCI2A/CCI2B) or compare output (Out2). |
| 77 | P2.2/TB1 | bidirectional | General-purpose digital I/O; Timer_B CCR1 capture input (CCI1A/CCI1B) or compare output (Out1). |
| 78 | P2.1/TB0 | bidirectional | General-purpose digital I/O; Timer_B CCR0 capture input (CCI0A/CCI0B) or compare output (Out0). |
| 79 | P2.0/TA2 | bidirectional | General-purpose digital I/O; Timer_A capture input CCI2A or compare output Out2. |
| 80 | P1.7/CA1 | bidirectional | General-purpose digital I/O or Comparator_A input. |
| 81 | P1.6/CA0 | bidirectional | General-purpose digital I/O or Comparator_A input. |
| 82 | P1.5/TACLK/ACLK | bidirectional | General-purpose digital I/O; Timer_A clock input TACLK or ACLK output divided by 1, 2, 4 or 8. |
| 83 | P1.4/TBCLK/SMCLK | bidirectional | General-purpose digital I/O; Timer_B input clock TBCLK or submain system clock SMCLK output. |
| 84 | P1.3/TBOUTH/SVSOUT | bidirectional | General-purpose digital I/O; TBOUTH switches all Timer_B PWM outputs to high impedance, or SVS comparator output. |
| 85 | P1.2/TA1 | bidirectional | General-purpose digital I/O; Timer_A capture input CCI1A or compare output Out1. |
| 86 | P1.1/TA0/MCLK | bidirectional | General-purpose digital I/O; Timer_A capture input CCI0B, MCLK output, or BSL receive. TA0 is only an input on this pin. |
| 87 | P1.0/TA0 | bidirectional | General-purpose digital I/O; Timer_A capture input CCI0A or compare output Out0, or BSL transmit. |
| 88 | XT2OUT | output | Output terminal of crystal oscillator XT2. |
| 89 | XT2IN | input | Input port for crystal oscillator XT2; only standard crystals can be connected. |
| 90 | TDO/TDI | bidirectional | Test data output port; TDO/TDI data output or programming data input terminal. |
| 91 | TDI/TCLK | input | Test data input or test clock input; the device protection fuse is connected to this pin. |
| 92 | TMS | input | Test mode select; used as input for device programming and test. |
| 93 | TCK | input | Test clock; clock input port for device programming and test. |
| 94 | RST/NMI | input | Reset input or nonmaskable interrupt input port. |
| 95 | P5.0/SVSIN | bidirectional | General-purpose digital I/O or analog input to the supply voltage supervisor. |
| 96 | A3.0+ | input | SD16_A positive analog input A3.0 (MSP430x47x4 only); leave open if unused. |
| 97 | A3.0− | input | SD16_A negative analog input A3.0 (MSP430x47x4 only); leave open if unused. |
| 98 | AVSS | power_in | Analog supply voltage, negative terminal. |
| 99 | DVSS1 | power_in | Digital supply voltage, negative terminal (ground). |
| 100 | AVCC | power_in | Analog supply voltage, positive terminal; must not power up prior to DVCC1/DVCC2. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | QFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |
CAD (KiCad official)
- Symbol:
MSP430F4794IPZR - Footprint:
Package_QFP:LQFP-100_14x14mm_P0.5mm - 3D model: QFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files:
msp430f4794ipzr-etched.step/msp430f4794ipzr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430f4794ipzr.step/msp430f4794ipzr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (84 pp, sha256
ddafac1ca61d1dc4, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).