component
MSP430F47193IPZR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
MSP430F47193IPZR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)
MSP430F47193IPZR from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0.0+ | input | SD16_A positive analog input A0.0; short unused analog input pairs and connect them to analog ground (AVSS). |
| 2 | A0.0- | input | SD16_A negative analog input A0.0; short unused analog input pairs and connect them to analog ground (AVSS). |
| 3 | A1.0+ | input | SD16_A positive analog input A1.0; short unused analog input pairs and connect them to analog ground (AVSS). |
| 4 | A1.0- | input | SD16_A negative analog input A1.0; short unused analog input pairs and connect them to analog ground (AVSS). |
| 5 | A2.0+ | input | SD16_A positive analog input A2.0; short unused analog input pairs and connect them to analog ground (AVSS). |
| 6 | A2.0- | input | SD16_A negative analog input A2.0; short unused analog input pairs and connect them to analog ground (AVSS). |
| 7 | AVSS | power_in | Analog supply voltage, negative terminal. |
| 8 | AVCC | power_in | Analog supply voltage, positive terminal; must not power up prior to DVCC1/DVCC2. |
| 9 | VREF | power_in | Input for an external reference voltage or internal reference voltage output (can be used as mid-voltage). |
| 10 | NC | unconnected | Not connected on MSP430F471x3 (A3.0+ exists only on x6/7); connect pin to analog ground (AVSS). |
| 11 | NC | unconnected | Not connected on MSP430F471x3 (A3.0- exists only on x6/7); connect pin to analog ground (AVSS). |
| 12 | NC | unconnected | Not connected on MSP430F471x3 (A4.0+ exists only on x6/7); connect pin to analog ground (AVSS). |
| 13 | NC | unconnected | Not connected on MSP430F471x3 (A4.0- exists only on x6/7); connect pin to analog ground (AVSS). |
| 14 | NC | unconnected | Not connected on MSP430F471x3 (A5.0+ exists only on x6/7); connect pin to analog ground (AVSS). |
| 15 | NC | unconnected | Not connected on MSP430F471x3 (A5.0- exists only on x6/7); connect pin to analog ground (AVSS). |
| 16 | NC | unconnected | Not connected on MSP430F471x3 (A6.0+ exists only on x7); connect pin to analog ground (AVSS). |
| 17 | NC | unconnected | Not connected on MSP430F471x3 (A6.0- exists only on x7); connect pin to analog ground (AVSS). |
| 18 | AVSS | power_in | Analog supply voltage, negative terminal. |
| 19 | P10.3/S0 | bidirectional | General-purpose digital I/O with LCD segment output S0. |
| 20 | P10.2/S1 | bidirectional | General-purpose digital I/O with LCD segment output S1. |
| 21 | P10.1/S2 | bidirectional | General-purpose digital I/O with LCD segment output S2. |
| 22 | P10.0/S3 | bidirectional | General-purpose digital I/O with LCD segment output S3. |
| 23 | P9.7/S4 | bidirectional | General-purpose digital I/O with LCD segment output S4. |
| 24 | P9.6/S5 | bidirectional | General-purpose digital I/O with LCD segment output S5. |
| 25 | P9.5/S6 | bidirectional | General-purpose digital I/O with LCD segment output S6. |
| 26 | P9.4/S7 | bidirectional | General-purpose digital I/O with LCD segment output S7. |
| 27 | P9.3/S8 | bidirectional | General-purpose digital I/O with LCD segment output S8. |
| 28 | P9.2/S9 | bidirectional | General-purpose digital I/O with LCD segment output S9. |
| 29 | P9.1/S10 | bidirectional | General-purpose digital I/O with LCD segment output S10. |
| 30 | P9.0/S11 | bidirectional | General-purpose digital I/O with LCD segment output S11. |
| 31 | P8.7/S12 | bidirectional | General-purpose digital I/O with LCD segment output S12. |
| 32 | P8.6/S13 | bidirectional | General-purpose digital I/O with LCD segment output S13. |
| 33 | P8.5/S14 | bidirectional | General-purpose digital I/O with LCD segment output S14. |
| 34 | P8.4/S15 | bidirectional | General-purpose digital I/O with LCD segment output S15. |
| 35 | P8.3/S16 | bidirectional | General-purpose digital I/O with LCD segment output S16. |
| 36 | P8.2/S17 | bidirectional | General-purpose digital I/O with LCD segment output S17. |
| 37 | P8.1/S18 | bidirectional | General-purpose digital I/O with LCD segment output S18. |
| 38 | P8.0/S19 | bidirectional | General-purpose digital I/O with LCD segment output S19. |
| 39 | P7.7/S20 | bidirectional | General-purpose digital I/O with LCD segment output S20. |
| 40 | P7.6/S21 | bidirectional | General-purpose digital I/O with LCD segment output S21. |
| 41 | P7.5/S22 | bidirectional | General-purpose digital I/O with LCD segment output S22. |
| 42 | P7.4/S23 | bidirectional | General-purpose digital I/O with LCD segment output S23. |
| 43 | P7.3/S24 | bidirectional | General-purpose digital I/O with LCD segment output S24. |
| 44 | P7.2/S25 | bidirectional | General-purpose digital I/O with LCD segment output S25. |
| 45 | P7.1/S26 | bidirectional | General-purpose digital I/O with LCD segment output S26. |
| 46 | P7.0/S27 | bidirectional | General-purpose digital I/O with LCD segment output S27. |
| 47 | P4.7/S28 | bidirectional | General-purpose digital I/O with LCD segment output S28. |
| 48 | P4.6/S29 | bidirectional | General-purpose digital I/O with LCD segment output S29. |
| 49 | P4.5/S30 | bidirectional | General-purpose digital I/O with LCD segment output S30. |
| 50 | P4.4/S31 | bidirectional | General-purpose digital I/O with LCD segment output S31. |
| 51 | P4.3/S32 | bidirectional | General-purpose digital I/O with LCD segment output S32. |
| 52 | P4.2/S33 | bidirectional | General-purpose digital I/O with LCD segment output S33. |
| 53 | P4.1/DMAE0/S34 | bidirectional | General-purpose digital I/O, DMA channel 0 external trigger, and LCD segment output S34. |
| 54 | P4.0/CAOUT/S35 | bidirectional | General-purpose digital I/O, Comparator_A output, and LCD segment output S35. |
| 55 | P5.0/SVSIN | bidirectional | General-purpose digital I/O and analog input to the supply voltage supervisor. |
| 56 | P5.1/COM0 | bidirectional | General-purpose digital I/O and LCD common output COM0 (COM0-3 are used for LCD backplanes). |
| 57 | P5.2/COM1 | bidirectional | General-purpose digital I/O and LCD common output COM1 (COM0-3 are used for LCD backplanes). |
| 58 | P5.3/COM2 | bidirectional | General-purpose digital I/O and LCD common output COM2 (COM0-3 are used for LCD backplanes). |
| 59 | P5.4/COM3 | bidirectional | General-purpose digital I/O and LCD common output COM3 (COM0-3 are used for LCD backplanes). |
| 60 | P5.5/R03 | bidirectional | General-purpose digital I/O and input port of the lowest analog LCD level (V5). |
| 61 | P5.6/LCDREF/R13 | bidirectional | General-purpose digital I/O, external reference voltage input for regulated LCD voltage, and input port of the third most positive analog LCD level (V4 or V3). |
| 62 | P5.7/R23 | bidirectional | General-purpose digital I/O and input port of the second most positive analog LCD level (V2). |
| 63 | LCDCAP/R33 | bidirectional | LCD capacitor connection and input/output port of the most positive analog LCD level (V1). |
| 64 | DVCC2 | power_in | Digital supply voltage, positive terminal. |
| 65 | XIN | input | Input port for crystal oscillator XT1; standard or watch crystals can be connected. |
| 66 | XOUT | output | Output terminal of crystal oscillator XT1. |
| 67 | DVSS2 | power_in | Digital supply voltage, negative terminal. |
| 68 | P3.7/TB2/S36 | bidirectional | General-purpose digital I/O, Timer_B3 CCR2 capture/compare (CCI2A/CCI2B input, Out2 output), and LCD segment output S36. |
| 69 | P3.6/TB1/S37 | bidirectional | General-purpose digital I/O, Timer_B3 CCR1 capture/compare (CCI1A/CCI1B input, Out1 output), and LCD segment output S37. |
| 70 | P3.5/TB0/S38 | bidirectional | General-purpose digital I/O, Timer_B3 CCR0 capture/compare (CCI0A/CCI0B input, Out0 output), and LCD segment output S38. |
| 71 | P3.4/TA2/S39 | bidirectional | General-purpose digital I/O, Timer_A capture input CCI2A or compare output Out2, and LCD segment output S39. |
| 72 | P3.3/UCB0CLK/UCA0STE | bidirectional | General-purpose digital I/O, USCI_B0 clock input/output, or USCI_A0 slave transmit enable. |
| 73 | P3.2/UCB0SOMI/UCB0SCL | bidirectional | General-purpose digital I/O, USCI_B0 slave out/master in in SPI mode, or SCL I2C clock in I2C mode. |
| 74 | P3.1/UCB0SIMO/UCB0SDA | bidirectional | General-purpose digital I/O, USCI_B0 slave in/master out in SPI mode, or SDA I2C data in I2C mode. |
| 75 | P3.0/UCB0STE/UCA0CLK | bidirectional | General-purpose digital I/O, USCI_B0 slave transmit enable, or USCI_A0 clock input/output. |
| 76 | P2.7/CA1 | bidirectional | General-purpose digital I/O and Comparator_A input CA1. |
| 77 | P2.6/CA0 | bidirectional | General-purpose digital I/O and Comparator_A input CA0. |
| 78 | P2.5/UCA0RXD/UCA0SOMI | bidirectional | General-purpose digital I/O, USCI_A0 receive data input in UART mode, or slave out/master in in SPI mode. |
| 79 | P2.4/UCA0TXD/UCA0SIMO | bidirectional | General-purpose digital I/O, USCI_A0 transmit data output in UART mode, or slave in/master out in SPI mode. |
| 80 | P2.3/UCB1CLK/UCA1STE | bidirectional | General-purpose digital I/O, USCI_B1 clock input/output, or USCI_A1 slave transmit enable. |
| 81 | P2.2/UCB1SOMI/UCB1SCL | bidirectional | General-purpose digital I/O, USCI_B1 slave out/master in in SPI mode, or SCL I2C clock in I2C mode. |
| 82 | P2.1/UCB1SIMO/UCB1SDA | bidirectional | General-purpose digital I/O, USCI_B1 slave in/master out in SPI mode, or SDA I2C data in I2C mode. |
| 83 | P2.0/UCB1STE/UCA1CLK | bidirectional | General-purpose digital I/O, USCI_B1 slave transmit enable, or USCI_A1 clock input/output. |
| 84 | P1.7/UCA1RXD/UCA1SOMI | bidirectional | General-purpose digital I/O, USCI_A1 receive data input in UART mode, or slave out/master in in SPI mode. |
| 85 | P1.6/UCA1TXD/UCA1SIMO | bidirectional | General-purpose digital I/O, USCI_A1 transmit data output in UART mode, or slave in/master out in SPI mode. |
| 86 | P1.5/TACLK/ACLK | bidirectional | General-purpose digital I/O, Timer_A clock input TACLK, or ACLK output (divided by 1, 2, 4, or 8). |
| 87 | P1.4/TBCLK/SMCLK | bidirectional | General-purpose digital I/O, Timer_B3 input clock TBCLK, or SMCLK submain system clock output. |
| 88 | P1.3/TBOUTH/SVSOUT | bidirectional | General-purpose digital I/O, high-impedance control for all Timer_B3 PWM outputs (TBOUTH), or SVS comparator output (SVSOUT). |
| 89 | P1.2/TA1 | bidirectional | General-purpose digital I/O and Timer_A capture input CCI1A or compare output Out1. |
| 90 | P1.1/TA0/MCLK | bidirectional | General-purpose digital I/O, Timer_A capture input CCI0B (TA0 is only an input on this pin), MCLK output, and BSL receive. |
| 91 | P1.0/TA0 | bidirectional | General-purpose digital I/O, Timer_A capture input CCI0A or compare output Out0, and BSL transmit. |
| 92 | DVCC1 | power_in | Digital supply voltage, positive terminal. |
| 93 | XT2OUT | output | Output terminal of crystal oscillator XT2. |
| 94 | XT2IN | input | Input port for crystal oscillator XT2; only standard crystals can be connected. |
| 95 | DVSS1 | power_in | Digital supply voltage, negative terminal. |
| 96 | TDO/TDI | bidirectional | Test data output port; TDO/TDI data output or programming data input terminal. |
| 97 | TDI/TCLK | input | Test data input or test clock input; the device protection fuse is connected to TDI/TCLK. |
| 98 | TMS | input | Test mode select; used as an input port for device programming and test. |
| 99 | TCK | input | Test clock; the clock input port for device programming and test. |
| 100 | RST/NMI | input | Reset input or nonmaskable interrupt input port. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |
CAD (KiCad official)
- Symbol:
MSP430F47193IPZR - Footprint:
Package_QFP:LQFP-100_14x14mm_P0.5mm - 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files:
msp430f47193ipzr-etched.step/msp430f47193ipzr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430f47193ipzr.step/msp430f47193ipzr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (92 pp, sha256
890f49d1d54dc9f3, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MSP430F47193IPZR
**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)
MSP430F47193IPZR from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0.0+ | input | SD16_A positive analog input A0.0; short unused analog input pairs and connect them to analog ground (AVSS). |
| 2 | A0.0- | input | SD16_A negative analog input A0.0; short unused analog input pairs and connect them to analog ground (AVSS). |
| 3 | A1.0+ | input | SD16_A positive analog input A1.0; short unused analog input pairs and connect them to analog ground (AVSS). |
| 4 | A1.0- | input | SD16_A negative analog input A1.0; short unused analog input pairs and connect them to analog ground (AVSS). |
| 5 | A2.0+ | input | SD16_A positive analog input A2.0; short unused analog input pairs and connect them to analog ground (AVSS). |
| 6 | A2.0- | input | SD16_A negative analog input A2.0; short unused analog input pairs and connect them to analog ground (AVSS). |
| 7 | AVSS | power_in | Analog supply voltage, negative terminal. |
| 8 | AVCC | power_in | Analog supply voltage, positive terminal; must not power up prior to DVCC1/DVCC2. |
| 9 | VREF | power_in | Input for an external reference voltage or internal reference voltage output (can be used as mid-voltage). |
| 10 | NC | unconnected | Not connected on MSP430F471x3 (A3.0+ exists only on x6/7); connect pin to analog ground (AVSS). |
| 11 | NC | unconnected | Not connected on MSP430F471x3 (A3.0- exists only on x6/7); connect pin to analog ground (AVSS). |
| 12 | NC | unconnected | Not connected on MSP430F471x3 (A4.0+ exists only on x6/7); connect pin to analog ground (AVSS). |
| 13 | NC | unconnected | Not connected on MSP430F471x3 (A4.0- exists only on x6/7); connect pin to analog ground (AVSS). |
| 14 | NC | unconnected | Not connected on MSP430F471x3 (A5.0+ exists only on x6/7); connect pin to analog ground (AVSS). |
| 15 | NC | unconnected | Not connected on MSP430F471x3 (A5.0- exists only on x6/7); connect pin to analog ground (AVSS). |
| 16 | NC | unconnected | Not connected on MSP430F471x3 (A6.0+ exists only on x7); connect pin to analog ground (AVSS). |
| 17 | NC | unconnected | Not connected on MSP430F471x3 (A6.0- exists only on x7); connect pin to analog ground (AVSS). |
| 18 | AVSS | power_in | Analog supply voltage, negative terminal. |
| 19 | P10.3/S0 | bidirectional | General-purpose digital I/O with LCD segment output S0. |
| 20 | P10.2/S1 | bidirectional | General-purpose digital I/O with LCD segment output S1. |
| 21 | P10.1/S2 | bidirectional | General-purpose digital I/O with LCD segment output S2. |
| 22 | P10.0/S3 | bidirectional | General-purpose digital I/O with LCD segment output S3. |
| 23 | P9.7/S4 | bidirectional | General-purpose digital I/O with LCD segment output S4. |
| 24 | P9.6/S5 | bidirectional | General-purpose digital I/O with LCD segment output S5. |
| 25 | P9.5/S6 | bidirectional | General-purpose digital I/O with LCD segment output S6. |
| 26 | P9.4/S7 | bidirectional | General-purpose digital I/O with LCD segment output S7. |
| 27 | P9.3/S8 | bidirectional | General-purpose digital I/O with LCD segment output S8. |
| 28 | P9.2/S9 | bidirectional | General-purpose digital I/O with LCD segment output S9. |
| 29 | P9.1/S10 | bidirectional | General-purpose digital I/O with LCD segment output S10. |
| 30 | P9.0/S11 | bidirectional | General-purpose digital I/O with LCD segment output S11. |
| 31 | P8.7/S12 | bidirectional | General-purpose digital I/O with LCD segment output S12. |
| 32 | P8.6/S13 | bidirectional | General-purpose digital I/O with LCD segment output S13. |
| 33 | P8.5/S14 | bidirectional | General-purpose digital I/O with LCD segment output S14. |
| 34 | P8.4/S15 | bidirectional | General-purpose digital I/O with LCD segment output S15. |
| 35 | P8.3/S16 | bidirectional | General-purpose digital I/O with LCD segment output S16. |
| 36 | P8.2/S17 | bidirectional | General-purpose digital I/O with LCD segment output S17. |
| 37 | P8.1/S18 | bidirectional | General-purpose digital I/O with LCD segment output S18. |
| 38 | P8.0/S19 | bidirectional | General-purpose digital I/O with LCD segment output S19. |
| 39 | P7.7/S20 | bidirectional | General-purpose digital I/O with LCD segment output S20. |
| 40 | P7.6/S21 | bidirectional | General-purpose digital I/O with LCD segment output S21. |
| 41 | P7.5/S22 | bidirectional | General-purpose digital I/O with LCD segment output S22. |
| 42 | P7.4/S23 | bidirectional | General-purpose digital I/O with LCD segment output S23. |
| 43 | P7.3/S24 | bidirectional | General-purpose digital I/O with LCD segment output S24. |
| 44 | P7.2/S25 | bidirectional | General-purpose digital I/O with LCD segment output S25. |
| 45 | P7.1/S26 | bidirectional | General-purpose digital I/O with LCD segment output S26. |
| 46 | P7.0/S27 | bidirectional | General-purpose digital I/O with LCD segment output S27. |
| 47 | P4.7/S28 | bidirectional | General-purpose digital I/O with LCD segment output S28. |
| 48 | P4.6/S29 | bidirectional | General-purpose digital I/O with LCD segment output S29. |
| 49 | P4.5/S30 | bidirectional | General-purpose digital I/O with LCD segment output S30. |
| 50 | P4.4/S31 | bidirectional | General-purpose digital I/O with LCD segment output S31. |
| 51 | P4.3/S32 | bidirectional | General-purpose digital I/O with LCD segment output S32. |
| 52 | P4.2/S33 | bidirectional | General-purpose digital I/O with LCD segment output S33. |
| 53 | P4.1/DMAE0/S34 | bidirectional | General-purpose digital I/O, DMA channel 0 external trigger, and LCD segment output S34. |
| 54 | P4.0/CAOUT/S35 | bidirectional | General-purpose digital I/O, Comparator_A output, and LCD segment output S35. |
| 55 | P5.0/SVSIN | bidirectional | General-purpose digital I/O and analog input to the supply voltage supervisor. |
| 56 | P5.1/COM0 | bidirectional | General-purpose digital I/O and LCD common output COM0 (COM0-3 are used for LCD backplanes). |
| 57 | P5.2/COM1 | bidirectional | General-purpose digital I/O and LCD common output COM1 (COM0-3 are used for LCD backplanes). |
| 58 | P5.3/COM2 | bidirectional | General-purpose digital I/O and LCD common output COM2 (COM0-3 are used for LCD backplanes). |
| 59 | P5.4/COM3 | bidirectional | General-purpose digital I/O and LCD common output COM3 (COM0-3 are used for LCD backplanes). |
| 60 | P5.5/R03 | bidirectional | General-purpose digital I/O and input port of the lowest analog LCD level (V5). |
| 61 | P5.6/LCDREF/R13 | bidirectional | General-purpose digital I/O, external reference voltage input for regulated LCD voltage, and input port of the third most positive analog LCD level (V4 or V3). |
| 62 | P5.7/R23 | bidirectional | General-purpose digital I/O and input port of the second most positive analog LCD level (V2). |
| 63 | LCDCAP/R33 | bidirectional | LCD capacitor connection and input/output port of the most positive analog LCD level (V1). |
| 64 | DVCC2 | power_in | Digital supply voltage, positive terminal. |
| 65 | XIN | input | Input port for crystal oscillator XT1; standard or watch crystals can be connected. |
| 66 | XOUT | output | Output terminal of crystal oscillator XT1. |
| 67 | DVSS2 | power_in | Digital supply voltage, negative terminal. |
| 68 | P3.7/TB2/S36 | bidirectional | General-purpose digital I/O, Timer_B3 CCR2 capture/compare (CCI2A/CCI2B input, Out2 output), and LCD segment output S36. |
| 69 | P3.6/TB1/S37 | bidirectional | General-purpose digital I/O, Timer_B3 CCR1 capture/compare (CCI1A/CCI1B input, Out1 output), and LCD segment output S37. |
| 70 | P3.5/TB0/S38 | bidirectional | General-purpose digital I/O, Timer_B3 CCR0 capture/compare (CCI0A/CCI0B input, Out0 output), and LCD segment output S38. |
| 71 | P3.4/TA2/S39 | bidirectional | General-purpose digital I/O, Timer_A capture input CCI2A or compare output Out2, and LCD segment output S39. |
| 72 | P3.3/UCB0CLK/UCA0STE | bidirectional | General-purpose digital I/O, USCI_B0 clock input/output, or USCI_A0 slave transmit enable. |
| 73 | P3.2/UCB0SOMI/UCB0SCL | bidirectional | General-purpose digital I/O, USCI_B0 slave out/master in in SPI mode, or SCL I2C clock in I2C mode. |
| 74 | P3.1/UCB0SIMO/UCB0SDA | bidirectional | General-purpose digital I/O, USCI_B0 slave in/master out in SPI mode, or SDA I2C data in I2C mode. |
| 75 | P3.0/UCB0STE/UCA0CLK | bidirectional | General-purpose digital I/O, USCI_B0 slave transmit enable, or USCI_A0 clock input/output. |
| 76 | P2.7/CA1 | bidirectional | General-purpose digital I/O and Comparator_A input CA1. |
| 77 | P2.6/CA0 | bidirectional | General-purpose digital I/O and Comparator_A input CA0. |
| 78 | P2.5/UCA0RXD/UCA0SOMI | bidirectional | General-purpose digital I/O, USCI_A0 receive data input in UART mode, or slave out/master in in SPI mode. |
| 79 | P2.4/UCA0TXD/UCA0SIMO | bidirectional | General-purpose digital I/O, USCI_A0 transmit data output in UART mode, or slave in/master out in SPI mode. |
| 80 | P2.3/UCB1CLK/UCA1STE | bidirectional | General-purpose digital I/O, USCI_B1 clock input/output, or USCI_A1 slave transmit enable. |
| 81 | P2.2/UCB1SOMI/UCB1SCL | bidirectional | General-purpose digital I/O, USCI_B1 slave out/master in in SPI mode, or SCL I2C clock in I2C mode. |
| 82 | P2.1/UCB1SIMO/UCB1SDA | bidirectional | General-purpose digital I/O, USCI_B1 slave in/master out in SPI mode, or SDA I2C data in I2C mode. |
| 83 | P2.0/UCB1STE/UCA1CLK | bidirectional | General-purpose digital I/O, USCI_B1 slave transmit enable, or USCI_A1 clock input/output. |
| 84 | P1.7/UCA1RXD/UCA1SOMI | bidirectional | General-purpose digital I/O, USCI_A1 receive data input in UART mode, or slave out/master in in SPI mode. |
| 85 | P1.6/UCA1TXD/UCA1SIMO | bidirectional | General-purpose digital I/O, USCI_A1 transmit data output in UART mode, or slave in/master out in SPI mode. |
| 86 | P1.5/TACLK/ACLK | bidirectional | General-purpose digital I/O, Timer_A clock input TACLK, or ACLK output (divided by 1, 2, 4, or 8). |
| 87 | P1.4/TBCLK/SMCLK | bidirectional | General-purpose digital I/O, Timer_B3 input clock TBCLK, or SMCLK submain system clock output. |
| 88 | P1.3/TBOUTH/SVSOUT | bidirectional | General-purpose digital I/O, high-impedance control for all Timer_B3 PWM outputs (TBOUTH), or SVS comparator output (SVSOUT). |
| 89 | P1.2/TA1 | bidirectional | General-purpose digital I/O and Timer_A capture input CCI1A or compare output Out1. |
| 90 | P1.1/TA0/MCLK | bidirectional | General-purpose digital I/O, Timer_A capture input CCI0B (TA0 is only an input on this pin), MCLK output, and BSL receive. |
| 91 | P1.0/TA0 | bidirectional | General-purpose digital I/O, Timer_A capture input CCI0A or compare output Out0, and BSL transmit. |
| 92 | DVCC1 | power_in | Digital supply voltage, positive terminal. |
| 93 | XT2OUT | output | Output terminal of crystal oscillator XT2. |
| 94 | XT2IN | input | Input port for crystal oscillator XT2; only standard crystals can be connected. |
| 95 | DVSS1 | power_in | Digital supply voltage, negative terminal. |
| 96 | TDO/TDI | bidirectional | Test data output port; TDO/TDI data output or programming data input terminal. |
| 97 | TDI/TCLK | input | Test data input or test clock input; the device protection fuse is connected to TDI/TCLK. |
| 98 | TMS | input | Test mode select; used as an input port for device programming and test. |
| 99 | TCK | input | Test clock; the clock input port for device programming and test. |
| 100 | RST/NMI | input | Reset input or nonmaskable interrupt input port. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |
## CAD (KiCad official)
- Symbol: `MSP430F47193IPZR`
- Footprint: `Package_QFP:LQFP-100_14x14mm_P0.5mm`
- 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files: `msp430f47193ipzr-etched.step` / `msp430f47193ipzr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430f47193ipzr.step` / `msp430f47193ipzr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430f47187) (92 pp, sha256 `890f49d1d54dc9f3`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/msp430f47193ipzr-datasheet.pdf)