component

MSP430F47173IPZR

Public Made by Adom

by adom

Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersmsp430f47173ipzrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers msp430f47173ipzr: viewers · Ray 1d ago
msp430f47173ipzr-etched.glb msp430f47173ipzr: factory component page (tier=lcsc) · Ray 1d ago
msp430f47173ipzr-etched.step msp430f47173ipzr: factory component page (tier=lcsc) · Ray 1d ago
msp430f47173ipzr-hero.glb msp430f47173ipzr: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
msp430f47173ipzr-hero.overlay.json Publish 0.1.0 · Ray 1d ago
msp430f47173ipzr.glb Publish 0.1.0 · Ray 1d ago
msp430f47173ipzr.kicad_mod Publish 0.1.0 · Ray 1d ago
msp430f47173ipzr.kicad_sym Publish 0.1.0 · Ray 1d ago
msp430f47173ipzr.lbr Publish 0.1.0 · Ray 1d ago
msp430f47173ipzr.step Publish 0.1.0 · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Initial commit: component/msp430f47173ipzr · Ray 1d ago

MSP430F47173IPZR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

MSP430F47173IPZR from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A0.0+ input SD16_A positive analog input A0.0; recommended to short unused analog input pairs to analog ground (AVSS).
2 A0.0- input SD16_A negative analog input A0.0; recommended to short unused analog input pairs to analog ground (AVSS).
3 A1.0+ input SD16_A positive analog input A1.0; recommended to short unused analog input pairs to analog ground (AVSS).
4 A1.0- input SD16_A negative analog input A1.0; recommended to short unused analog input pairs to analog ground (AVSS).
5 A2.0+ input SD16_A positive analog input A2.0; recommended to short unused analog input pairs to analog ground (AVSS).
6 A2.0- input SD16_A negative analog input A2.0; recommended to short unused analog input pairs to analog ground (AVSS).
7 AVSS power_in Analog supply voltage, negative terminal.
8 AVCC power_in Analog supply voltage, positive terminal; must not power up prior to DVCC1/DVCC2.
9 VREF power_in Input for an external reference voltage or internal reference voltage output (can be used as mid-voltage).
10 NC unconnected Not connected on MSP430F471x3; connect pin to analog ground (AVSS).
11 NC unconnected Not connected on MSP430F471x3; connect pin to analog ground (AVSS).
12 NC unconnected Not connected on MSP430F471x3; connect pin to analog ground (AVSS).
13 NC unconnected Not connected on MSP430F471x3; connect pin to analog ground (AVSS).
14 NC unconnected Not connected on MSP430F471x3; connect pin to analog ground (AVSS).
15 NC unconnected Not connected on MSP430F471x3; connect pin to analog ground (AVSS).
16 NC unconnected Not connected on MSP430F471x3; connect pin to analog ground (AVSS).
17 NC unconnected Not connected on MSP430F471x3; connect pin to analog ground (AVSS).
18 AVSS power_in Analog supply voltage, negative terminal.
19 P10.3/S0 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 0.
20 P10.2/S1 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 1.
21 P10.1/S2 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 2.
22 P10.0/S3 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 3.
23 P9.7/S4 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 4.
24 P9.6/S5 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 5.
25 P9.5/S6 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 6.
26 P9.4/S7 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 7.
27 P9.3/S8 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 8.
28 P9.2/S9 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 9.
29 P9.1/S10 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 10.
30 P9.0/S11 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 11.
31 P8.7/S12 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 12.
32 P8.6/S13 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 13.
33 P8.5/S14 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 14.
34 P8.4/S15 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 15.
35 P8.3/S16 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 16.
36 P8.2/S17 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 17.
37 P8.1/S18 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 18.
38 P8.0/S19 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 19.
39 P7.7/S20 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 20.
40 P7.6/S21 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 21.
41 P7.5/S22 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 22.
42 P7.4/S23 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 23.
43 P7.3/S24 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 24.
44 P7.2/S25 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 25.
45 P7.1/S26 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 26.
46 P7.0/S27 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 27.
47 P4.7/S28 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 28.
48 P4.6/S29 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 29.
49 P4.5/S30 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 30.
50 P4.4/S31 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 31.
51 P4.3/S32 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 32.
52 P4.2/S33 bidirectional General-purpose digital I/O with Schmitt trigger; LCD segment output 33.
53 P4.1/DMAE0/S34 bidirectional General-purpose digital I/O with Schmitt trigger; DMA channel 0 external trigger; LCD segment output 34.
54 P4.0/CAOUT/S35 bidirectional General-purpose digital I/O with Schmitt trigger; Comparator_A output; LCD segment output 35.
55 P5.0/SVSIN bidirectional General-purpose digital I/O with Schmitt trigger; analog input to the supply voltage supervisor.
56 P5.1/COM0 bidirectional General-purpose digital I/O with Schmitt trigger; LCD common output COM0 (COM0-3 used for LCD backplanes).
57 P5.2/COM1 bidirectional General-purpose digital I/O with Schmitt trigger; LCD common output COM1 (COM0-3 used for LCD backplanes).
58 P5.3/COM2 bidirectional General-purpose digital I/O with Schmitt trigger; LCD common output COM2 (COM0-3 used for LCD backplanes).
59 P5.4/COM3 bidirectional General-purpose digital I/O with Schmitt trigger; LCD common output COM3 (COM0-3 used for LCD backplanes).
60 P5.5/R03 bidirectional General-purpose digital I/O with Schmitt trigger; input port of the lowest analog LCD level (V5).
61 P5.6/LCDREF/R13 bidirectional General-purpose digital I/O with Schmitt trigger; external reference voltage input for regulated LCD voltage; input port of the third most positive analog LCD level (V4 or V3).
62 P5.7/R23 bidirectional General-purpose digital I/O with Schmitt trigger; input port of the second most positive analog LCD level (V2).
63 LCDCAP/R33 passive LCD capacitor connection; input/output port of the most positive analog LCD level (V1).
64 DVCC2 power_in Digital supply voltage, positive terminal.
65 XIN input Input port for crystal oscillator XT1; standard or watch crystals can be connected.
66 XOUT output Output terminal of crystal oscillator XT1.
67 DVSS2 power_in Digital supply voltage, negative terminal.
68 P3.7/TB2/S36 bidirectional General-purpose digital I/O with Schmitt trigger; Timer_B3 CCR2 capture/compare output; LCD segment output 36.
69 P3.6/TB1/S37 bidirectional General-purpose digital I/O with Schmitt trigger; Timer_B3 CCR1 capture/compare output; LCD segment output 37.
70 P3.5/TB0/S38 bidirectional General-purpose digital I/O with Schmitt trigger; Timer_B3 CCR0 capture/compare output; LCD segment output 38.
71 P3.4/TA2/S39 bidirectional General-purpose digital I/O with Schmitt trigger; Timer_A CCI2A input / Out2 output; LCD segment output 39.
72 P3.3/UCB0CLK/UCA0STE bidirectional General-purpose digital I/O with Schmitt trigger; USCI_B0 clock input/output; USCI_A0 slave transmit enable.
73 P3.2/UCB0SOMI/UCB0SCL bidirectional General-purpose digital I/O with Schmitt trigger; USCI_B0 slave out/master in in SPI mode; SCL I2C clock in I2C mode.
74 P3.1/UCB0SIMO/UCB0SDA bidirectional General-purpose digital I/O with Schmitt trigger; USCI_B0 slave in/master out in SPI mode; SDA I2C data in I2C mode.
75 P3.0/UCB0STE/UCA0CLK bidirectional General-purpose digital I/O with Schmitt trigger; USCI_B0 slave transmit enable; USCI_A0 clock input/output.
76 P2.7/CA1 bidirectional General-purpose digital I/O with Schmitt trigger; Comparator_A input CA1.
77 P2.6/CA0 bidirectional General-purpose digital I/O with Schmitt trigger; Comparator_A input CA0.
78 P2.5/UCA0RXD/UCA0SOMI bidirectional General-purpose digital I/O with Schmitt trigger; USCI_A0 receive data input in UART mode; slave out/master in in SPI mode.
79 P2.4/UCA0TXD/UCA0SIMO bidirectional General-purpose digital I/O with Schmitt trigger; USCI_A0 transmit data output in UART mode; slave in/master out in SPI mode.
80 P2.3/UCB1CLK/UCA1STE bidirectional General-purpose digital I/O with Schmitt trigger; USCI_B1 clock input/output; USCI_A1 slave transmit enable.
81 P2.2/UCB1SOMI/UCB1SCL bidirectional General-purpose digital I/O with Schmitt trigger; USCI_B1 slave out/master in in SPI mode; SCL I2C clock in I2C mode.
82 P2.1/UCB1SIMO/UCB1SDA bidirectional General-purpose digital I/O with Schmitt trigger; USCI_B1 slave in/master out in SPI mode; SDA I2C data in I2C mode.
83 P2.0/UCB1STE/UCA1CLK bidirectional General-purpose digital I/O with Schmitt trigger; USCI_B1 slave transmit enable; USCI_A1 clock input/output.
84 P1.7/UCA1RXD/UCA1SOMI bidirectional General-purpose digital I/O with Schmitt trigger; USCI_A1 receive data input in UART mode; slave out/master in in SPI mode.
85 P1.6/UCA1TXD/UCA1SIMO bidirectional General-purpose digital I/O with Schmitt trigger; USCI_A1 transmit data output in UART mode; slave in/master out in SPI mode.
86 P1.5/TACLK/ACLK bidirectional General-purpose digital I/O with Schmitt trigger; Timer_A clock input TACLK; ACLK output (divided by 1, 2, 4, or 8).
87 P1.4/TBCLK/SMCLK bidirectional General-purpose digital I/O with Schmitt trigger; input clock TBCLK for Timer_B3; submain system clock SMCLK output.
88 P1.3/TBOUTH/SVSOUT bidirectional General-purpose digital I/O with Schmitt trigger; high-impedance switch for all Timer_B3 PWM outputs (TB0 to TB2); SVS comparator output.
89 P1.2/TA1 bidirectional General-purpose digital I/O with Schmitt trigger; Timer_A capture input CCI1A and compare output Out1.
90 P1.1/TA0/MCLK bidirectional General-purpose digital I/O with Schmitt trigger; Timer_A capture input CCI0B; MCLK output; TA0 is only an input on this pin; BSL receive.
91 P1.0/TA0 bidirectional General-purpose digital I/O with Schmitt trigger; Timer_A capture input CCI0A and compare output Out0; BSL transmit.
92 DVCC1 power_in Digital supply voltage, positive terminal.
93 XT2OUT output Output terminal of crystal oscillator XT2.
94 XT2IN input Input port for crystal oscillator XT2; only standard crystals can be connected.
95 DVSS1 power_in Digital supply voltage, negative terminal.
96 TDO/TDI bidirectional Test data output port; TDO/TDI data output or programming data input terminal.
97 TDI/TCLK input Test data input or test clock input; the device protection fuse is connected to TDI/TCLK.
98 TMS input Test mode select; TMS is used as an input port for device programming and test.
99 TCK input Test clock; TCK is the clock input port for device programming and test.
100 RST/NMI input Reset input or nonmaskable interrupt input port.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: MSP430F47173IPZR
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: msp430f47173ipzr-etched.step / msp430f47173ipzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430f47173ipzr.step / msp430f47173ipzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (92 pp, sha256 890f49d1d54dc9f3, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF