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MSP430F436IPZR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSP430F436IPZR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

MSP430F436IPZR from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DVCC1 power_in Digital supply voltage, positive terminal.
2 P6.3/A3 bidirectional General-purpose digital I/O / analog input a3 of the 12-bit ADC.
3 P6.4/A4 bidirectional General-purpose digital I/O / analog input a4 of the 12-bit ADC.
4 P6.5/A5 bidirectional General-purpose digital I/O / analog input a5 of the 12-bit ADC.
5 P6.6/A6 bidirectional General-purpose digital I/O / analog input a6 of the 12-bit ADC.
6 P6.7/A7/SVSIN bidirectional General-purpose digital I/O / analog input a7 of the 12-bit ADC, and analog input to the brownout and supply voltage supervisor.
7 VREF+ power_in Output of positive terminal of the reference voltage in the ADC.
8 XIN input Input port for crystal oscillator XT1; standard or watch crystals can be connected.
9 XOUT output Output terminal of crystal oscillator XT1.
10 VeREF+ input Input for an external reference voltage to the ADC.
11 VREF−/VeREF− power_in Negative terminal for the ADC reference voltage, from the internal reference or an external applied reference voltage.
12 P5.1/S0 bidirectional General-purpose digital I/O / LCD segment output 0.
13 P5.0/S1 bidirectional General-purpose digital I/O / LCD segment output 1.
14 S2 output LCD segment output 2.
15 S3 output LCD segment output 3.
16 S4 output LCD segment output 4.
17 S5 output LCD segment output 5.
18 S6 output LCD segment output 6.
19 S7 output LCD segment output 7.
20 S8 output LCD segment output 8.
21 S9 output LCD segment output 9.
22 S10 output LCD segment output 10.
23 S11 output LCD segment output 11.
24 S12 output LCD segment output 12.
25 S13 output LCD segment output 13.
26 S14 output LCD segment output 14.
27 S15 output LCD segment output 15.
28 S16 output LCD segment output 16.
29 S17 output LCD segment output 17.
30 S18 output LCD segment output 18 (this PZ pin is LCD-only; the ADC12CLK function is on pin 72).
31 S19 output LCD segment output 19 (this PZ pin is LCD-only; the CAOUT function is on pin 73).
32 S20 output LCD segment output 20.
33 S21 output LCD segment output 21.
34 S22 output LCD segment output 22.
35 S23 output LCD segment output 23.
36 S24 output LCD segment output 24.
37 S25 output LCD segment output 25.
38 S26 output LCD segment output 26.
39 S27 output LCD segment output 27.
40 S28 output LCD segment output 28.
41 S29 output LCD segment output 29.
42 S30 output LCD segment output 30.
43 S31 output LCD segment output 31.
44 S32 output LCD segment output 32.
45 S33 output LCD segment output 33.
46 P4.7/S34 bidirectional General-purpose digital I/O / LCD segment output 34.
47 P4.6/S35 bidirectional General-purpose digital I/O / LCD segment output 35.
48 P4.5/S36 bidirectional General-purpose digital I/O / LCD segment output 36.
49 P4.4/S37 bidirectional General-purpose digital I/O / LCD segment output 37.
50 P4.3/S38 bidirectional General-purpose digital I/O / LCD segment output 38.
51 P4.2/S39 bidirectional General-purpose digital I/O / LCD segment output 39.
52 COM0 output LCD backplane common output 0 (COM0-3 are used for LCD backplanes).
53 P5.2/COM1 bidirectional General-purpose digital I/O / LCD backplane common output COM1.
54 P5.3/COM2 bidirectional General-purpose digital I/O / LCD backplane common output COM2.
55 P5.4/COM3 bidirectional General-purpose digital I/O / LCD backplane common output COM3.
56 R03 input Input port of the fourth positive (lowest) analog LCD level (V5).
57 P5.5/R13 bidirectional General-purpose digital I/O / input port of the third most positive analog LCD level (V4 or V3).
58 P5.6/R23 bidirectional General-purpose digital I/O / input port of the second most positive analog LCD level (V2).
59 P5.7/R33 bidirectional General-purpose digital I/O / output port of the most positive analog LCD level (V1).
60 DVCC2 power_in Digital supply voltage, positive terminal.
61 DVSS2 power_in Digital supply voltage, negative terminal.
62 P4.1 bidirectional General-purpose digital I/O.
63 P4.0 bidirectional General-purpose digital I/O.
64 P3.7 bidirectional General-purpose digital I/O.
65 P3.6 bidirectional General-purpose digital I/O.
66 P3.5 bidirectional General-purpose digital I/O.
67 P3.4 bidirectional General-purpose digital I/O.
68 P3.3/UCLK0 bidirectional General-purpose digital I/O / external clock input in USART0 UART or SPI mode, clock output in USART0 SPI mode.
69 P3.2/SOMI0 bidirectional General-purpose digital I/O / slave out, master in of USART0 SPI mode.
70 P3.1/SIMO0 bidirectional General-purpose digital I/O / slave in, master out of USART0 SPI mode.
71 P3.0/STE0 bidirectional General-purpose digital I/O / slave transmit enable of USART0 SPI mode.
72 P2.7/ADC12CLK bidirectional General-purpose digital I/O / conversion clock of the 12-bit ADC.
73 P2.6/CAOUT bidirectional General-purpose digital I/O / Comparator_A output.
74 P2.5/URXD0 bidirectional General-purpose digital I/O / receive data input of USART0 UART mode.
75 P2.4/UTXD0 bidirectional General-purpose digital I/O / transmit data output of USART0 UART mode.
76 P2.3/TB2 bidirectional General-purpose digital I/O / Timer_B3 CCR2 capture input (CCI2A/CCI2B) or compare output (Out2).
77 P2.2/TB1 bidirectional General-purpose digital I/O / Timer_B3 CCR1 capture input (CCI1A/CCI1B) or compare output (Out1).
78 P2.1/TB0 bidirectional General-purpose digital I/O / Timer_B3 CCR0 capture input (CCI0A/CCI0B) or compare output (Out0).
79 P2.0/TA2 bidirectional General-purpose digital I/O / Timer_A capture input CCI2A or compare output Out2.
80 P1.7/CA1 bidirectional General-purpose digital I/O / Comparator_A input.
81 P1.6/CA0 bidirectional General-purpose digital I/O / Comparator_A input.
82 P1.5/TACLK/ACLK bidirectional General-purpose digital I/O / Timer_A clock input TACLK or ACLK output (divided by 1, 2, 4, or 8).
83 P1.4/TBCLK/SMCLK bidirectional General-purpose digital I/O / Timer_B3 input clock TBCLK or submain system clock SMCLK output.
84 P1.3/TBOUTH/SVSOUT bidirectional General-purpose digital I/O / switches all Timer_B3 PWM outputs TB0 to TB2 to high impedance, or SVS comparator output.
85 P1.2/TA1 bidirectional General-purpose digital I/O / Timer_A capture input CCI1A or compare output Out1.
86 P1.1/TA0/MCLK bidirectional General-purpose digital I/O / Timer_A capture input CCI0B or MCLK output; TA0 is only an input on this pin; also BSL receive.
87 P1.0/TA0 bidirectional General-purpose digital I/O / Timer_A capture input CCI0A or compare output Out0; also BSL transmit.
88 XT2OUT output Output terminal of crystal oscillator XT2.
89 XT2IN input Input port for crystal oscillator XT2; only standard crystals can be connected.
90 TDO/TDI bidirectional Test data output port; TDO/TDI data output or programming data input terminal.
91 TDI/TCLK input Test data input or test clock input; the device protection fuse is connected to TDI/TCLK.
92 TMS input Test mode select; TMS is used as an input port for device programming and test.
93 TCK input Test clock; TCK is the clock input port for device programming and test.
94 RST/NMI input Reset input or nonmaskable interrupt input port.
95 P6.0/A0 bidirectional General-purpose digital I/O / analog input a0 of the 12-bit ADC.
96 P6.1/A1 bidirectional General-purpose digital I/O / analog input a1 of the 12-bit ADC.
97 P6.2/A2 bidirectional General-purpose digital I/O / analog input a2 of the 12-bit ADC.
98 AVSS power_in Analog supply voltage, negative terminal; supplies SVS, brownout, oscillator, comparator_A, ADC12, port 1, and LCD resistive divider circuitry.
99 DVSS1 power_in Digital supply voltage, negative terminal.
100 AVCC power_in Analog supply voltage, positive terminal; supplies SVS, brownout, oscillator, comparator_A, ADC12, port 1, and LCD resistive divider circuitry; must not power up prior to DVCC1/DVCC2.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: MSP430F436IPZR
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: msp430f436ipzr-etched.step / msp430f436ipzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430f436ipzr.step / msp430f436ipzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (89 pp, sha256 ff6c7ef212cfbf3f, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF