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MSP430F4250IRGZR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSP430F4250IRGZR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-48-EP(7x7)

MSP430F4250IRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DVSS power_in Digital supply voltage, negative terminal.
2 XIN input Input terminal of crystal oscillator XT1.
3 XOUT output Output terminal of crystal oscillator XT1.
4 AVSS power_in Analog supply voltage, negative terminal.
5 AVCC power_in Analog supply voltage, positive terminal.
6 VREF power_in Analog reference voltage.
7 P6.0/A0+ bidirectional General-purpose digital I/O and analog input A0+.
8 P6.1/A0− bidirectional General-purpose digital I/O and analog input A0−.
9 P6.2/A1+ bidirectional General-purpose digital I/O and analog input A1+.
10 P6.3/A1− bidirectional General-purpose digital I/O and analog input A1−.
11 P6.4 bidirectional General-purpose digital I/O.
12 P6.5 bidirectional General-purpose digital I/O.
13 P6.6 bidirectional General-purpose digital I/O.
14 P6.7 bidirectional General-purpose digital I/O.
15 P1.7/A2+ bidirectional General-purpose digital I/O and analog input A2+.
16 P1.6/A2− bidirectional General-purpose digital I/O and analog input A2−.
17 P1.5/TACLK/ACLK/A3+ bidirectional General-purpose digital I/O; Timer_A clock input TACLK, ACLK output (divided by 1, 2, 4, or 8), and analog input A3+.
18 P1.4/A3−/DAC0 bidirectional General-purpose digital I/O, analog input A3−, and DAC12 output.
19 P1.3/TA2/A4+ bidirectional General-purpose digital I/O, Timer_A capture CCI2A / compare Out2 output, and analog input A4+.
20 P1.2/TA1/A4− bidirectional General-purpose digital I/O, Timer_A capture CCI1A / compare Out1 output, and analog input A4−.
21 P1.1/TA0/MCLK bidirectional General-purpose digital I/O, Timer_A capture CCI0B, and MCLK output; TA0 is only an input on this pin, and it also serves as BSL receive.
22 P1.0/TA0 bidirectional General-purpose digital I/O, Timer_A capture CCI0A input and compare Out0 output; also serves as BSL transmit.
23 LCDREF/R13 input External LCD reference voltage input and input port of the third most positive analog LCD level (V4 or V3).
24 LCDCAP/R23 passive Capacitor connection for the LCD charge pump; also the input port of the second most positive analog LCD level (V2).
25 P5.1/S0 bidirectional General-purpose digital I/O and LCD segment output 0.
26 P5.0/S1 bidirectional General-purpose digital I/O and LCD segment output 1.
27 P5.5/S2 bidirectional General-purpose digital I/O and LCD segment output 2.
28 P5.6/S3 bidirectional General-purpose digital I/O and LCD segment output 3.
29 P5.7/S4 bidirectional General-purpose digital I/O and LCD segment output 4.
30 S5 output LCD segment output 5.
31 P2.7/S6 bidirectional General-purpose digital I/O and LCD segment output 6.
32 P2.6/S7 bidirectional General-purpose digital I/O and LCD segment output 7.
33 P2.5/S8 bidirectional General-purpose digital I/O and LCD segment output 8.
34 P2.4/S9 bidirectional General-purpose digital I/O and LCD segment output 9.
35 P2.3/S10 bidirectional General-purpose digital I/O and LCD segment output 10.
36 P2.2/S11 bidirectional General-purpose digital I/O and LCD segment output 11.
37 P2.1/S12 bidirectional General-purpose digital I/O and LCD segment output 12.
38 P2.0/S13 bidirectional General-purpose digital I/O and LCD segment output 13.
39 COM0 output Common output; COM0−3 are used for LCD backplanes.
40 P5.2/COM1 bidirectional General-purpose digital I/O and common output COM1; COM0−3 are used for LCD backplanes.
41 P5.3/COM2 bidirectional General-purpose digital I/O and common output COM2; COM0−3 are used for LCD backplanes.
42 P5.4/COM3 bidirectional General-purpose digital I/O and common output COM3; COM0−3 are used for LCD backplanes.
43 TDO/TDI bidirectional Test data output port; carries TDO/TDI data output or programming data input.
44 TDI/TCLK input Test data input or test clock input; the device protection fuse is connected to this pin.
45 TMS input Test mode select; used as an input port for device programming and test.
46 TCK input Test clock; the clock input port for device programming and test.
47 RST/NMI input General-purpose digital I/O, reset input, or nonmaskable interrupt input port.
48 DVCC power_in Digital supply voltage, positive terminal.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Embedded Processors & Controllers
Pins 49

CAD (KiCad official)

  • Symbol: MSP430F4250IRGZR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: msp430f4250irgzr-etched.step / msp430f4250irgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430f4250irgzr.step / msp430f4250irgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (67 pp, sha256 f9d3a21a0486f369, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF