# MSP430F4132IPMR

**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

MSP430F4132IPMR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P6.1/UCB0SOMI/UCB0SCL | bidirectional | General-purpose digital I/O pin; USCI B0 slave out/master in in SPI mode or SCL I2C clock in I2C mode (64-pin package only). |
| 2 | P6.2/UCB0SIMO/UCB0SDA | bidirectional | General-purpose digital I/O pin; USCI B0 slave in/master out in SPI mode or SDA I2C data in I2C mode (64-pin package only). |
| 3 | P6.3/UCB0STE/UCA0CLK/A3/CA5/VeREF-/VREF- | bidirectional | General-purpose digital I/O pin; USCI B0 slave transmit enable or USCI A0 clock input/output; ADC10 analog input A3 and negative reference; Comparator_A input 5. |
| 4 | P6.4/UCB0CLK/UCA0STE/A4/CA6/VeREF+/VREF+ | bidirectional | General-purpose digital I/O pin; USCI B0 clock input/output or USCI A0 slave transmit enable; ADC10 analog input A4 and positive reference; Comparator_A input 6. |
| 5 | P6.5/UCA0RXD/UCA0SOMI/A5 | bidirectional | General-purpose digital I/O pin; USCI A0 receive data input in UART mode or slave data out/master in in SPI mode; ADC10 analog input A5. |
| 6 | P6.6/UCA0TXD/UCA0SIMO/A6 | bidirectional | General-purpose digital I/O pin; USCI A0 transmit data output in UART mode or slave data in/master out in SPI mode; ADC10 analog input A6. |
| 7 | DVCC | power_in | Digital supply voltage, positive terminal; supplies all digital parts. |
| 8 | XIN | input | Input port for crystal oscillator XT1; standard or watch crystals can be connected. |
| 9 | XOUT | output | Output port for crystal oscillator XT1; standard or watch crystals can be connected. |
| 10 | DVSS | power_in | Digital supply voltage, negative terminal (ground); supplies all digital parts. |
| 11 | P6.7/A7/CA7/SVSIN | bidirectional | General-purpose digital I/O pin; ADC10 analog input A7; Comparator_A input 7; SVS input (64-pin package only). |
| 12 | P4.7/ADC10CLK/S0 | bidirectional | General-purpose digital I/O pin; ADC10 conversion clock output; LCD segment output S0. |
| 13 | P4.6/S1 | bidirectional | General-purpose digital I/O pin; LCD segment output S1. |
| 14 | P4.5/S2 | bidirectional | General-purpose digital I/O pin; LCD segment output S2. |
| 15 | P4.4/S3 | bidirectional | General-purpose digital I/O pin; LCD segment output S3. |
| 16 | P4.3/S4 | bidirectional | General-purpose digital I/O pin; LCD segment output S4. |
| 17 | P4.2/S5 | bidirectional | General-purpose digital I/O pin; LCD segment output S5. |
| 18 | P4.1/S6 | bidirectional | General-purpose digital I/O pin; LCD segment output S6. |
| 19 | P4.0/S7 | bidirectional | General-purpose digital I/O pin; LCD segment output S7. |
| 20 | P2.7/S8 | bidirectional | General-purpose digital I/O pin; LCD segment output S8. |
| 21 | P2.6/S9 | bidirectional | General-purpose digital I/O pin; LCD segment output S9. |
| 22 | P2.5/S10 | bidirectional | General-purpose digital I/O pin; LCD segment output S10. |
| 23 | P2.4/S11 | bidirectional | General-purpose digital I/O pin; LCD segment output S11. |
| 24 | P2.3/TA1.4/S12 | bidirectional | General-purpose digital I/O pin; Timer1_A5 compare Out4 output; LCD segment output S12. |
| 25 | P2.2/TA1.3/S13 | bidirectional | General-purpose digital I/O pin; Timer1_A5 compare Out3 output; LCD segment output S13. |
| 26 | P2.1/TA1.2/S14 | bidirectional | General-purpose digital I/O pin; Timer1_A5 compare Out2 output; LCD segment output S14. |
| 27 | P2.0/TA1.1/S15 | bidirectional | General-purpose digital I/O pin; Timer1_A5 compare Out1 output; LCD segment output S15. |
| 28 | P3.7/S16 | bidirectional | General-purpose digital I/O pin; LCD segment output S16. |
| 29 | P3.6/S17 | bidirectional | General-purpose digital I/O pin; LCD segment output S17. |
| 30 | P3.5/S18 | bidirectional | General-purpose digital I/O pin; LCD segment output S18. |
| 31 | P3.4/CAOUT/S19 | bidirectional | General-purpose digital I/O pin; Comparator_A output; LCD segment output S19. |
| 32 | P3.3/TA0.0/TA1CLK/S20 | bidirectional | General-purpose digital I/O pin; Timer0_A3 compare Out0 output; Timer1_A5 TACLK clock input; LCD segment output S20. |
| 33 | P3.2/TA1.4/S21 | bidirectional | General-purpose digital I/O pin; Timer1_A5 capture CCI4A input, compare Out4 output; LCD segment output S21. |
| 34 | P3.1/TA1.3/S22 | bidirectional | General-purpose digital I/O pin; Timer1_A5 capture CCI3A input, compare Out3 output; LCD segment output S22. |
| 35 | P3.0/TA1.2/S23 | bidirectional | General-purpose digital I/O pin; Timer1_A5 capture CCI2A input, compare Out2 output; LCD segment output S23. |
| 36 | P5.7/COM0 | bidirectional | General-purpose digital I/O pin; common output COM0 for LCD backplanes (COM0-3). |
| 37 | P5.6/COM1 | bidirectional | General-purpose digital I/O pin; common output COM1 for LCD backplanes (COM0-3). |
| 38 | P5.5/COM2 | bidirectional | General-purpose digital I/O pin; common output COM2 for LCD backplanes (COM0-3). |
| 39 | P5.4/COM3 | bidirectional | General-purpose digital I/O pin; common output COM3 for LCD backplanes (COM0-3). |
| 40 | P5.3/R03 | bidirectional | General-purpose digital I/O pin; input port of the fourth most positive analog LCD level (V1). |
| 41 | P5.2/LCDREF/R13 | bidirectional | General-purpose digital I/O pin; external LCD reference voltage input; input port of the third most positive analog LCD level (V3 or V2). |
| 42 | P5.1/R23 | bidirectional | General-purpose digital I/O pin; input port of the second most positive analog LCD level (V3). |
| 43 | LCDCAP/R33 | bidirectional | Capacitor connection for LCD charge pump; input port of the most positive analog LCD level (V4). |
| 44 | P5.0/TA1.1/S24 | bidirectional | General-purpose digital I/O pin; Timer1_A5 capture CCI1A input, compare Out1 output; LCD segment output S24. |
| 45 | P7.6/TA0.2/S25 | bidirectional | General-purpose digital I/O pin; Timer0_A3 capture CCI2A input, compare Out2 output; LCD segment output S25. |
| 46 | P1.7/TA0CLK/CAOUT/CA1 | bidirectional | General-purpose digital I/O pin; Timer0_A3 TACLK clock input; Comparator_A output; Comparator_A input 1. |
| 47 | P1.6/ACLK/CA0 | bidirectional | General-purpose digital I/O pin; ACLK signal output; Comparator_A input 0. |
| 48 | P1.5/TA0CLK/CAOUT/S26 | bidirectional | General-purpose digital I/O pin; Timer0_A3 TACLK clock input; Comparator_A output; LCD segment output S26. |
| 49 | P1.4/TA1.0/S27 | bidirectional | General-purpose digital I/O pin; Timer1_A5 capture CCI0A input, compare Out0 output; LCD segment output S27. |
| 50 | P1.3/TA1.0/SVSOUT/S28 | bidirectional | General-purpose digital I/O pin; Timer1_A5 capture CCI0B input; SVS comparator output; LCD segment output S28. |
| 51 | P1.2/TA0.1/S29 | bidirectional | General-purpose digital I/O pin; Timer0_A3 capture CCI1A input, compare Out1 output; LCD segment output S29. |
| 52 | P1.1/TA0.0/MCLK/S30 | bidirectional | General-purpose digital I/O pin; Timer0_A3 capture CCI0B input; MCLK signal output; LCD segment output S30. |
| 53 | P1.0/TA0.0/S31 | bidirectional | General-purpose digital I/O pin; Timer0_A3 capture CCI0A input, compare Out0 output; LCD segment output S31. |
| 54 | P7.0/TDO/TDI/S32 | bidirectional | General-purpose digital I/O pin; JTAG test data output or test data input during programming and test; LCD segment output S32. |
| 55 | P7.1/TDI/TCLK/S33 | bidirectional | General-purpose digital I/O pin; JTAG test data input or test clock input during programming and test; LCD segment output S33. |
| 56 | P7.2/TMS/S34 | bidirectional | General-purpose digital I/O pin; JTAG test mode select, input terminal for device programming and test; LCD segment output S34. |
| 57 | P7.3/TCK/S35 | bidirectional | General-purpose digital I/O pin; test clock input for device programming and test; LCD segment output S35. |
| 58 | RST/NMI/SBWTDIO | input | Reset or nonmaskable interrupt input; Spy-Bi-Wire test data input/output during programming and test. |
| 59 | TEST/SBWTCLK | input | Selects test mode for JTAG pins on Port 7; the device protection fuse is connected to TEST. |
| 60 | P7.4/TA1.4/A0/CA2 | bidirectional | General-purpose digital I/O pin; Timer1_A5 capture CCI4B input, compare Out4 output; ADC10 analog input A0; Comparator_A input 2. |
| 61 | P7.5/TA1.3/A1/CA3 | bidirectional | General-purpose digital I/O pin; Timer1_A5 capture CCI3B input, compare Out3 output; ADC10 analog input A1; Comparator_A input 3. |
| 62 | AVSS | power_in | Analog supply voltage, negative terminal (ground). |
| 63 | P6.0/TA1.2/A2/CA4 | bidirectional | General-purpose digital I/O pin; Timer1_A5 compare Out2 output; ADC10 analog input A2; Comparator_A input 4 (64-pin package only). |
| 64 | AVCC | power_in | Analog supply voltage, positive terminal. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |

## CAD (KiCad official)

- Symbol: `MSP430F4132IPMR`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `msp430f4132ipmr-etched.step` / `msp430f4132ipmr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430f4132ipmr.step` / `msp430f4132ipmr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430f4152) (85 pp, sha256 `0b610cd707374514`, retrieved 2026-10-07, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/msp430f4132ipmr-datasheet.pdf)