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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

MSP430f249TPMR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

MSP430f249TPMR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DVCC	power_in	Digital power supply voltage positive terminal; powers all digital components, 1.8V to 3.6V operating range.
2	P6.3/A3	bidirectional	Port P6.3 general purpose digital I/O or analog input A3 for 12-bit ADC.
3	P6.4/A4	bidirectional	Port P6.4 general purpose digital I/O or analog input A4 for 12-bit ADC.
4	P6.5/A5	bidirectional	Port P6.5 general purpose digital I/O or analog input A5 for 12-bit ADC.
5	P6.6/A6	bidirectional	Port P6.6 general purpose digital I/O or analog input A6 for 12-bit ADC.
6	P6.7/A7/SVSIN	bidirectional	Port P6.7 general purpose digital I/O, analog input A7 for 12-bit ADC, or SVS comparator input.
7	VREF+	power_in	ADC12 reference voltage positive output; internal buffered reference with typical output 1.5V or 2.5V selectable.
8	XIN	input	Crystal oscillator XT1 input; supports standard or watch crystals at 32768 Hz or 0.4 to 16 MHz in HF mode.
9	XOUT	output	Crystal oscillator XT1 output; supports standard or watch crystals.
10	VeREF+	input	External reference voltage positive input for ADC12; voltage range 1.4V to AVCC.
11	VREF-/VeREF-	power_in	Reference voltage negative terminal input for internal or external reference sources; range 0V to 1.2V.
12	P1.0/TACLK/CAOUT	bidirectional	Port P1.0 general purpose digital I/O, Timer_A clock input, or Comparator_A input.
13	P1.1/TA0	bidirectional	Port P1.1 general purpose digital I/O, Timer_A capture input CCI0A or compare output TA0, or BSL transmit.
14	P1.2/TA1	bidirectional	Port P1.2 general purpose digital I/O, Timer_A capture input CCI1A or compare output TA1.
15	P1.3/TA2	bidirectional	Port P1.3 general purpose digital I/O, Timer_A capture input CCI2A or compare output TA2.
16	P1.4/SMCLK	bidirectional	Port P1.4 general purpose digital I/O or subsystem clock SMCLK output.
17	P1.5/TA0	bidirectional	Port P1.5 general purpose digital I/O or Timer_A compare output TA0.
18	P1.6/TA1	bidirectional	Port P1.6 general purpose digital I/O or Timer_A compare output TA1.
19	P1.7/TA2	bidirectional	Port P1.7 general purpose digital I/O or Timer_A compare output TA2.
20	P2.0/ACLK/CA2	bidirectional	Port P2.0 general purpose digital I/O, auxiliary clock ACLK output, or Comparator_A input.
21	P2.1/TAINCLK/CA3	bidirectional	Port P2.1 general purpose digital I/O, Timer_A INCLK clock signal, or Comparator_A input.
22	P2.2/CAOUT/TA0/CA4	bidirectional	Port P2.2 general purpose digital I/O, Timer_A capture CCI0B input or TA0 output, Comparator_A output, or BSL receive.
23	P2.3/CA0/TA1	bidirectional	Port P2.3 general purpose digital I/O, Timer_A compare output TA1, or Comparator_A input.
24	P2.4/CA1/TA2	bidirectional	Port P2.4 general purpose digital I/O, Timer_A compare output TA2, or Comparator_A input.
25	P2.5/ROSC/CA5	bidirectional	Port P2.5 general purpose digital I/O, external resistor input defining DCO nominal frequency, or Comparator_A input.
26	P2.6/ADC12CLK/CA6	bidirectional	Port P2.6 general purpose digital I/O, 12-bit ADC conversion clock input, or Comparator_A input.
27	P2.7/TA0/CA7	bidirectional	Port P2.7 general purpose digital I/O, Timer_A compare output TA0, or Comparator_A input.
28	P3.0/UCB0STE/UCA0CLK	bidirectional	Port P3.0 general purpose digital I/O, USCI_B0 slave transmit enable, or USCI_A0 clock input/output.
29	P3.1/UCB0SIMO/UCB0SDA	bidirectional	Port P3.1 general purpose digital I/O, USCI_B0 slave input/master output in SPI mode or SDA in I2C mode.
30	P3.2/UCB0SOMI/UCB0SCL	bidirectional	Port P3.2 general purpose digital I/O, USCI_B0 slave output/master input in SPI mode or SCL in I2C mode.
31	P3.3/UCB0CLK/UCA0STE	bidirectional	Port P3.3 general purpose digital I/O, USCI_B0 clock input/output, or USCI_A0 slave transmit enable.
32	P3.4/UCA0TXD/UCA0SIMO	bidirectional	Port P3.4 general purpose digital I/O, USCI_A0 transmit data output in UART or slave data input/master output in SPI.
33	P3.5/UCA0RXD/UCA0SOMI	bidirectional	Port P3.5 general purpose digital I/O, USCI_A0 receive data input in UART or slave data output/master input in SPI.
34	P3.6/UCA1TXD/UCA1SIMO	bidirectional	Port P3.6 general purpose digital I/O, USCI_A1 transmit data output in UART or slave data input/master output in SPI.
35	P3.7/UCA1RXD/UCA1SOMI	bidirectional	Port P3.7 general purpose digital I/O, USCI_A1 receive data input in UART or slave data output/master input in SPI.
36	P4.0/TB0	bidirectional	Port P4.0 general purpose digital I/O or Timer_B capture input CCI0A/B and compare output TB0.
37	P4.1/TB1	bidirectional	Port P4.1 general purpose digital I/O or Timer_B capture input CCI1A/B and compare output TB1.
38	P4.2/TB2	bidirectional	Port P4.2 general purpose digital I/O or Timer_B capture input CCI2A/B and compare output TB2.
39	P4.3/TB3	bidirectional	Port P4.3 general purpose digital I/O or Timer_B capture input CCI3A/B and compare output TB3.
40	P4.4/TB4	bidirectional	Port P4.4 general purpose digital I/O or Timer_B capture input CCI4A/B and compare output TB4.
41	P4.5/TB5	bidirectional	Port P4.5 general purpose digital I/O or Timer_B capture input CCI5A/B and compare output TB5.
42	P4.6/TB6	bidirectional	Port P4.6 general purpose digital I/O or Timer_B capture input CCI6A and compare output TB6.
43	P4.7/TBCLK	bidirectional	Port P4.7 general purpose digital I/O or Timer_B clock signal input TBCLK.
44	P5.0/UCB1STE/UCA1CLK	bidirectional	Port P5.0 general purpose digital I/O, USCI_B1 slave transmit enable, or USCI_A1 clock input/output.
45	P5.1/UCB1SIMO/UCB1SDA	bidirectional	Port P5.1 general purpose digital I/O, USCI_B1 slave input/master output in SPI mode or SDA in I2C mode.
46	P5.2/UCB1SOMI/UCB1SCL	bidirectional	Port P5.2 general purpose digital I/O, USCI_B1 slave output/master input in SPI mode or SCL in I2C mode.
47	P5.3/UCB1CLK/UCA1STE	bidirectional	Port P5.3 general purpose digital I/O, USCI_B1 clock input/output, or USCI_A1 slave transmit enable.
48	P5.4/MCLK	bidirectional	Port P5.4 general purpose digital I/O or master system clock MCLK output.
49	P5.5/SMCLK	bidirectional	Port P5.5 general purpose digital I/O or subsystem clock SMCLK output.
50	P5.6/ACLK	bidirectional	Port P5.6 general purpose digital I/O or auxiliary clock ACLK output.
51	P5.7/TBOUTH/SVSOUT	bidirectional	Port P5.7 general purpose digital I/O, Timer_B high output control for TB0-TB6 PWM to high impedance, or SVS comparator output.
52	XT2OUT	output	Crystal oscillator XT2 output for external crystal; supports 0.4 to 16 MHz depending on configuration.
53	XT2IN	input	Crystal oscillator XT2 input for external crystal or logic level oscillator input; supports 0.4 to 16 MHz.
54	TDO/TDI	bidirectional	Test data output or JTAG programming data input; used for device test and flash memory programming.
55	TDI/TCLK	input	Test data input or test clock input; device protection fuse is connected to this pin for JTAG operations.
56	TMS	input	Test mode select input for JTAG; used as input port for device programming and test operations.
57	TCK	input	Test clock input for JTAG; provides clock for device programming test and bootloader startup operations.
58	RST/NMI	input	Reset input, non-maskable interrupt input, or bootloader startup; requires 2 µs minimum pulse width.
59	P6.0/A0	bidirectional	Port P6.0 general purpose digital I/O or analog input A0 for 12-bit ADC.
60	P6.1/A1	bidirectional	Port P6.1 general purpose digital I/O or analog input A1 for 12-bit ADC.
61	P6.2/A2	bidirectional	Port P6.2 general purpose digital I/O or analog input A2 for 12-bit ADC.
62	AVSS	power_in	Analog power supply voltage negative terminal; provides ground reference for ADC12 analog circuitry.
63	DVSS	power_in	Digital power supply voltage negative terminal; provides ground reference for all digital components.
64	AVCC	power_in	Analog power supply voltage positive terminal; powers ADC12 analog circuitry, 1.8V to 3.6V operating range.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	LQFP-64(10x10)
Category	Embedded Processors & Controllers
Pins	64

CAD (KiCad official)

Symbol: MSP430f249TPMR
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: msp430f249tpmr-etched.step / msp430f249tpmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430f249tpmr.step / msp430f249tpmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (102 pp, sha256 841108068ef96d3c, retrieved 2026-09-24, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF