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MSP430F247TRGCR

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Texas Instruments Microcontroller Units (MCUs/MPUs/SOCs), VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSP430F247TRGCR

Texas Instruments · Microcontroller Units (MCUs/MPUs/SOCs) · VQFN-64-EP(9x9)

MSP430F247TRGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DVCC power_in Positive digital supply terminal that powers all digital parts; AVCC and DVCC should come from the same supply, with at most 0.3 V difference during power-up, and VCC is 1.8 V to 3.6 V during program execution.
2 P6.3/A3 bidirectional General-purpose digital I/O and ADC12 analog input A3.
3 P6.4/A4 bidirectional General-purpose digital I/O and ADC12 analog input A4.
4 P6.5/A5 bidirectional General-purpose digital I/O and ADC12 analog input A5.
5 P6.6/A6 bidirectional General-purpose digital I/O and ADC12 analog input A6.
6 P6.7/A7/SVSIN bidirectional General-purpose digital I/O, ADC12 analog input A7, and SVS input (VLD = 15).
7 VREF+ power_in Output of the positive ADC12 reference voltage generated by the internal reference.
8 XIN input Input to crystal oscillator XT1; a standard or watch-type crystal can be connected.
9 XOUT output Output of crystal oscillator XT1; a standard or watch-type crystal can be connected.
10 VeREF+ input Input for an external positive reference voltage for the ADC12.
11 VREF-/VeREF- power_in Negative reference terminal, selecting either the internal reference or an externally applied reference.
12 P1.0/TACLK/CAOUT bidirectional General-purpose digital I/O with Timer_A TACLK clock input and Comparator_A function.
13 P1.1/TA0 bidirectional General-purpose digital I/O with Timer_A CCI0A capture input and Out0 compare output, and BSL transmit function.
14 P1.2/TA1 bidirectional General-purpose digital I/O with Timer_A CCI1A capture input and Out1 compare output.
15 P1.3/TA2 bidirectional General-purpose digital I/O with Timer_A CCI2A capture input and Out2 compare output.
16 P1.4/SMCLK bidirectional General-purpose digital I/O with SMCLK signal output.
17 P1.5/TA0 bidirectional General-purpose digital I/O with Timer_A Out0 compare output.
18 P1.6/TA1 bidirectional General-purpose digital I/O with Timer_A Out1 compare output.
19 P1.7/TA2 bidirectional General-purpose digital I/O with Timer_A Out2 compare output.
20 P2.0/ACLK/CA2 bidirectional General-purpose digital I/O with ACLK output and Comparator_A input CA2.
21 P2.1/TAINCLK/CA3 bidirectional General-purpose digital I/O with Timer_A INCLK clock input and Comparator_A input CA3.
22 P2.2/CAOUT/TA0/CA4 bidirectional General-purpose digital I/O with Timer_A CCI0B capture input, Comparator_A output, BSL receive function, and Comparator_A input CA4.
23 P2.3/CA0/TA1 bidirectional General-purpose digital I/O with Timer_A Out1 compare output and Comparator_A input CA0.
24 P2.4/CA1/TA2 bidirectional General-purpose digital I/O with Timer_A Out2 compare output and Comparator_A input CA1.
25 P2.5/ROSC/CA5 bidirectional General-purpose digital I/O with input for the external resistor that sets the nominal DCO frequency, and Comparator_A input CA5.
26 P2.6/ADC12CLK/CA6 bidirectional General-purpose digital I/O with ADC12 conversion clock output and Comparator_A input CA6.
27 P2.7/TA0/CA7 bidirectional General-purpose digital I/O with Timer_A Out0 compare output and Comparator_A input CA7.
28 P3.0/UCB0STE/UCA0CLK bidirectional General-purpose digital I/O with USCI_B0 slave transmit enable and USCI_A0 clock input/output (direction set by the USCI module).
29 P3.1/UCB0SIMO/UCB0SDA bidirectional General-purpose digital I/O with USCI_B0 SPI slave-in/master-out and I2C SDA data function.
30 P3.2/UCB0SOMI/UCB0SCL bidirectional General-purpose digital I/O with USCI_B0 SPI slave-out/master-in and I2C SCL clock function; in I2C mode the output only drives logic 0 to VSS.
31 P3.3/UCB0CLK/UCA0STE bidirectional General-purpose digital I/O with USCI_B0 clock input/output and USCI_A0 slave transmit enable.
32 P3.4/UCA0TXD/UCA0SIMO bidirectional General-purpose digital I/O with USCI_A0 UART transmit data output and SPI slave-in/master-out.
33 P3.5/UCA0RXD/UCA0SOMI bidirectional General-purpose digital I/O with USCI_A0 UART receive data input and SPI slave-out/master-in.
34 P3.6/UCA1TXD/UCA1SIMO bidirectional General-purpose digital I/O with USCI_A1 UART transmit data output and SPI slave-in/master-out.
35 P3.7/UCA1RXD/UCA1SOMI bidirectional General-purpose digital I/O with USCI_A1 UART receive data input and SPI slave-out/master-in.
36 P4.0/TB0 bidirectional General-purpose digital I/O with Timer_B CCI0A/CCI0B capture inputs and Out0 compare output.
37 P4.1/TB1 bidirectional General-purpose digital I/O with Timer_B CCI1A/CCI1B capture inputs and Out1 compare output.
38 P4.2/TB2 bidirectional General-purpose digital I/O with Timer_B CCI2A/CCI2B capture inputs and Out2 compare output.
39 P4.3/TB3 bidirectional General-purpose digital I/O with Timer_B CCI3A/CCI3B capture inputs and Out3 compare output.
40 P4.4/TB4 bidirectional General-purpose digital I/O with Timer_B CCI4A/CCI4B capture inputs and Out4 compare output.
41 P4.5/TB5 bidirectional General-purpose digital I/O with Timer_B CCI5A/CCI5B capture inputs and Out5 compare output.
42 P4.6/TB6 bidirectional General-purpose digital I/O with Timer_B CCI6A capture input and Out6 compare output.
43 P4.7/TBCLK bidirectional General-purpose digital I/O with Timer_B TBCLK clock input.
44 P5.0/UCB1STE/UCA1CLK bidirectional General-purpose digital I/O with USCI_B1 slave transmit enable and USCI_A1 clock input/output.
45 P5.1/UCB1SIMO/UCB1SDA bidirectional General-purpose digital I/O with USCI_B1 SPI slave-in/master-out and I2C SDA data function.
46 P5.2/UCB1SOMI/UCB1SCL bidirectional General-purpose digital I/O with USCI_B1 SPI slave-out/master-in and I2C SCL clock function.
47 P5.3/UCB1CLK/UCA1STE bidirectional General-purpose digital I/O with USCI_B1 clock input/output and USCI_A1 slave transmit enable.
48 P5.4/MCLK bidirectional General-purpose digital I/O with main system clock MCLK output.
49 P5.5/SMCLK bidirectional General-purpose digital I/O with subsystem clock SMCLK output.
50 P5.6/ACLK bidirectional General-purpose digital I/O with auxiliary clock ACLK output.
51 P5.7/TBOUTH/SVSOUT bidirectional General-purpose digital I/O that, via Timer_B TBOUTH, switches all PWM outputs (TB0 to TB6) to high impedance, and also serves as SVS comparator output.
52 XT2OUT output Output terminal of crystal oscillator XT2.
53 XT2IN input Input terminal of crystal oscillator XT2.
54 TDO/TDI bidirectional JTAG test data output, or programming data input terminal.
55 TDI/TCLK input JTAG test data input or test clock input; the device protection fuse is connected to this pin.
56 TMS input JTAG test mode select, used as an input port for device programming and test.
57 TCK input JTAG test clock; the clock input port for device programming, test, and bootloader start.
58 RST/NMI input Reset input, non-maskable interrupt input, or bootloader start (in flash devices).
59 P6.0/A0 bidirectional General-purpose digital I/O and ADC12 analog input A0.
60 P6.1/A1 bidirectional General-purpose digital I/O and ADC12 analog input A1.
61 P6.2/A2 bidirectional General-purpose digital I/O and ADC12 analog input A2.
62 AVSS power_in Negative analog supply terminal, supplying only the analog section of the ADC12; AVSS and DVSS should be at the same potential.
63 DVSS power_in Negative digital supply terminal that supplies all digital parts (ground).
64 AVCC power_in Positive analog supply terminal, supplying only the analog section of the ADC12; should be supplied from the same source as DVCC.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-64-EP(9x9)
Category Single Chip Microcomputer/Microcontroller
Pins 65

CAD (KiCad official)

  • Symbol: MSP430F247TRGCR
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: msp430f247trgcr-etched.step / msp430f247trgcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430f247trgcr.step / msp430f247trgcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (102 pp, sha256 841108068ef96d3c, retrieved 2026-10-12, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF