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MSP430F2471TRGCR

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Texas Instruments Microcontroller Units (MCUs/MPUs/SOCs), VQFN-64-EP(9x9). Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

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MSP430F2471TRGCR

Texas Instruments · Microcontroller Units (MCUs/MPUs/SOCs) · VQFN-64-EP(9x9)

MSP430F2471TRGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DVCC power_in Digital supply voltage, positive terminal, supplying all digital parts; VCC is 1.8 V to 3.6 V during program execution.
2 P6.3/A3 bidirectional General-purpose digital I/O P6.3, also 12-bit ADC analog input A3.
3 P6.4/A4 bidirectional General-purpose digital I/O P6.4, also 12-bit ADC analog input A4.
4 P6.5/A5 bidirectional General-purpose digital I/O P6.5, also 12-bit ADC analog input A5.
5 P6.6/A6 bidirectional General-purpose digital I/O P6.6, also 12-bit ADC analog input A6.
6 P6.7/A7/SVSIN bidirectional General-purpose digital I/O P6.7, also 12-bit ADC analog input A7 and SVS input (SVSIN, VLD=15).
7 VREF+ output Positive ADC12 reference voltage output of the internal reference (1.5 V or 2.5 V); requires the external capacitor specified in the datasheet (10 µF tantalum plus 100 nF ceramic for INL/DNL testing).
8 XIN input Input to crystal oscillator XT1; accepts a standard or watch crystal.
9 XOUT output Output of crystal oscillator XT1; accepts a standard or watch crystal.
10 VeREF+ input Input for an external positive reference voltage for ADC12, from 1.4 V up to AVCC.
11 VREF-/VeREF- input Negative reference terminal selecting the internal reference or an externally applied reference (external range 0 V to 1.2 V).
12 P1.0/TACLK/CAOUT bidirectional General-purpose digital I/O P1.0, also Timer_A TACLK clock input and Comparator_A input per the pin table.
13 P1.1/TA0 bidirectional General-purpose digital I/O P1.1, also Timer_A CCI0A capture input, Out0 compare output, and BSL transmit.
14 P1.2/TA1 bidirectional General-purpose digital I/O P1.2, also Timer_A CCI1A capture input and Out1 compare output.
15 P1.3/TA2 bidirectional General-purpose digital I/O P1.3, also Timer_A CCI2A capture input and Out2 compare output.
16 P1.4/SMCLK bidirectional General-purpose digital I/O P1.4, also SMCLK signal output.
17 P1.5/TA0 bidirectional General-purpose digital I/O P1.5, also Timer_A Out0 compare output.
18 P1.6/TA1 bidirectional General-purpose digital I/O P1.6, also Timer_A Out1 compare output.
19 P1.7/TA2 bidirectional General-purpose digital I/O P1.7, also Timer_A Out2 compare output.
20 P2.0/ACLK/CA2 bidirectional General-purpose digital I/O P2.0, also ACLK output and Comparator_A input CA2.
21 P2.1/TAINCLK/CA3 bidirectional General-purpose digital I/O P2.1, also Timer_A INCLK clock signal and Comparator_A input CA3.
22 P2.2/CAOUT/TA0/CA4 bidirectional General-purpose digital I/O P2.2, also Timer_A CCI0B capture input, Comparator_A output, BSL receive, and Comparator_A input CA4.
23 P2.3/CA0/TA1 bidirectional General-purpose digital I/O P2.3, also Timer_A Out1 output and Comparator_A input CA0.
24 P2.4/CA1/TA2 bidirectional General-purpose digital I/O P2.4, also Timer_A Out2 output and Comparator_A input CA1.
25 P2.5/ROSC/CA5 bidirectional General-purpose digital I/O P2.5, also input for the external resistor ROSC that sets the nominal DCO frequency, and Comparator_A input CA5.
26 P2.6/ADC12CLK/CA6 bidirectional General-purpose digital I/O P2.6, also ADC12 conversion clock and Comparator_A input CA6.
27 P2.7/TA0/CA7 bidirectional General-purpose digital I/O P2.7, also Timer_A Out0 compare output and Comparator_A input CA7.
28 P3.0/UCB0STE/UCA0CLK bidirectional General-purpose digital I/O P3.0, also USCI_B0 slave transmit enable and USCI_A0 clock input/output.
29 P3.1/UCB0SIMO/UCB0SDA bidirectional General-purpose digital I/O P3.1, also USCI_B0 SPI slave-in/master-out or I2C data SDA.
30 P3.2/UCB0SOMI/UCB0SCL bidirectional General-purpose digital I/O P3.2, also USCI_B0 SPI slave-out/master-in or I2C clock SCL.
31 P3.3/UCB0CLK/UCA0STE bidirectional General-purpose digital I/O P3.3, also USCI_B0 clock input/output and USCI_A0 slave transmit enable.
32 P3.4/UCA0TXD/UCA0SIMO bidirectional General-purpose digital I/O P3.4, also USCI_A0 UART transmit data output or SPI slave-in/master-out.
33 P3.5/UCA0RXD/UCA0SOMI bidirectional General-purpose digital I/O P3.5, also USCI_A0 UART receive data input or SPI slave-out/master-in.
34 P3.6/UCA1TXD/UCA1SIMO bidirectional General-purpose digital I/O P3.6, also USCI_A1 UART transmit data output or SPI slave-in/master-out.
35 P3.7/UCA1RXD/UCA1SOMI bidirectional General-purpose digital I/O P3.7, also USCI_A1 UART receive data input or SPI slave-out/master-in.
36 P4.0/TB0 bidirectional General-purpose digital I/O P4.0, also Timer_B capture inputs CCI0A/CCI0B and Out0 compare output.
37 P4.1/TB1 bidirectional General-purpose digital I/O P4.1, also Timer_B capture inputs CCI1A/CCI1B and Out1 compare output.
38 P4.2/TB2 bidirectional General-purpose digital I/O P4.2, also Timer_B capture inputs CCI2A/CCI2B and Out2 compare output.
39 P4.3/TB3 bidirectional General-purpose digital I/O P4.3, also Timer_B capture inputs CCI3A/CCI3B and Out3 compare output.
40 P4.4/TB4 bidirectional General-purpose digital I/O P4.4, also Timer_B capture inputs CCI4A/CCI4B and Out4 compare output.
41 P4.5/TB5 bidirectional General-purpose digital I/O P4.5, also Timer_B capture inputs CCI5A/CCI5B and Out5 compare output.
42 P4.6/TB6 bidirectional General-purpose digital I/O P4.6, also Timer_B capture input CCI6A and Out6 compare output.
43 P4.7/TBCLK bidirectional General-purpose digital I/O P4.7, also Timer_B TBCLK clock input.
44 P5.0/UCB1STE/UCA1CLK bidirectional General-purpose digital I/O P5.0, also USCI_B1 slave transmit enable and USCI_A1 clock input/output.
45 P5.1/UCB1SIMO/UCB1SDA bidirectional General-purpose digital I/O P5.1, also USCI_B1 SPI slave-in/master-out or I2C data SDA.
46 P5.2/UCB1SOMI/UCB1SCL bidirectional General-purpose digital I/O P5.2, also USCI_B1 SPI slave-out/master-in or I2C clock SCL.
47 P5.3/UCB1CLK/UCA1STE bidirectional General-purpose digital I/O P5.3, also USCI_B1 clock input/output and USCI_A1 slave transmit enable.
48 P5.4/MCLK bidirectional General-purpose digital I/O P5.4, also master system clock MCLK output.
49 P5.5/SMCLK bidirectional General-purpose digital I/O P5.5, also subsystem clock SMCLK output.
50 P5.6/ACLK bidirectional General-purpose digital I/O P5.6, also auxiliary clock ACLK output.
51 P5.7/TBOUTH/SVSOUT bidirectional General-purpose digital I/O P5.7, also switches all Timer_B PWM outputs (TB0 to TB6) to high impedance and carries the SVS comparator output.
52 XT2OUT output Output terminal of crystal oscillator XT2.
53 XT2IN input Input terminal of crystal oscillator XT2.
54 TDO/TDI bidirectional JTAG test data output; also the programming data input terminal, and the test data input is used during fuse blow.
55 TDI/TCLK input JTAG test data input or test clock input; the device protection fuse is connected to this pin.
56 TMS input JTAG test mode select, used as an input port for device programming and test.
57 TCK input JTAG test clock input for device programming, test and bootloader start.
58 RST/NMI input Reset input, non-maskable interrupt input, or bootloader start (in flash devices).
59 P6.0/A0 bidirectional General-purpose digital I/O P6.0, also 12-bit ADC analog input A0.
60 P6.1/A1 bidirectional General-purpose digital I/O P6.1, also 12-bit ADC analog input A1.
61 P6.2/A2 bidirectional General-purpose digital I/O P6.2, also 12-bit ADC analog input A2.
62 AVSS power_in Analog supply voltage negative terminal, supplying only the analog part of ADC12; AVSS=DVSS=VSS=0 V.
63 DVSS power_in Digital supply voltage negative terminal, supplying all digital parts; 0 V.
64 AVCC power_in Positive analog supply voltage, supplying only the analog part of ADC12; ADC12 requires 2.2 V to 3.6 V and AVCC should be the same supply as DVCC.
65 QFN pad (DVSS) power_in Exposed QFN thermal pad, not a numbered pin in the pin table; the datasheet recommends connecting it to DVSS and it must be soldered to the board.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-64-EP(9x9)
Category Single Chip Microcomputer/Microcontroller
Pins 65

CAD (KiCad official)

  • Symbol: MSP430F2471TRGCR
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: msp430f2471trgcr-etched.step / msp430f2471trgcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430f2471trgcr.step / msp430f2471trgcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (102 pp, sha256 841108068ef96d3c, retrieved 2026-10-21, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF