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MSP430F235TPM
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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Datasheet
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README
markdownMSP430F235TPM
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
MSP430F235TPM from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DVCC | power_in | Digital supply voltage, positive terminal, supplying all digital parts; recommended VCC is 1.8 V to 3.6 V and AVCC should be supplied from the same source as DVCC. |
| 2 | P6.3/A3 | bidirectional | General-purpose digital I/O P6.3, or 12-bit ADC analog input A3. |
| 3 | P6.4/A4 | bidirectional | General-purpose digital I/O P6.4, or 12-bit ADC analog input A4. |
| 4 | P6.5/A5 | bidirectional | General-purpose digital I/O P6.5, or 12-bit ADC analog input A5. |
| 5 | P6.6/A6 | bidirectional | General-purpose digital I/O P6.6, or 12-bit ADC analog input A6. |
| 6 | P6.7/A7/SVSIN | bidirectional | General-purpose digital I/O P6.7, 12-bit ADC analog input A7, or SVS input. |
| 7 | VREF+ | power_out | Positive output of the ADC12 reference voltage (internal reference). |
| 8 | XIN | input | Input to crystal oscillator XT1; can connect a standard crystal or a watch crystal. |
| 9 | XOUT | output | Output of crystal oscillator XT1; can connect a standard crystal or a watch crystal. |
| 10 | VeREF+ | input | Input for an external positive reference voltage for the ADC12; VeREF+ must be greater than VREF-/VeREF- and within 1.4 V to AVCC. |
| 11 | VREF-/VeREF- | power_in | Negative reference terminal for either the internal reference or an externally applied reference voltage; external VREF-/VeREF- range is 0 V to 1.2 V. |
| 12 | P1.0/TACLK/CAOUT | bidirectional | General-purpose digital I/O P1.0, or Timer_A TACLK clock input, or Comparator_A output. |
| 13 | P1.1/TA0 | bidirectional | General-purpose digital I/O P1.1, or Timer_A CCI0A capture input / Out0 output, and BSL transmit. |
| 14 | P1.2/TA1 | bidirectional | General-purpose digital I/O P1.2, or Timer_A CCI1A capture input / Out1 output. |
| 15 | P1.3/TA2 | bidirectional | General-purpose digital I/O P1.3, or Timer_A CCI2A capture input / Out2 output. |
| 16 | P1.4/SMCLK | bidirectional | General-purpose digital I/O P1.4, or SMCLK subsystem clock output. |
| 17 | P1.5/TA0 | bidirectional | General-purpose digital I/O P1.5, or Timer_A Out0 output. |
| 18 | P1.6/TA1 | bidirectional | General-purpose digital I/O P1.6, or Timer_A Out1 output. |
| 19 | P1.7/TA2 | bidirectional | General-purpose digital I/O P1.7, or Timer_A Out2 output. |
| 20 | P2.0/ACLK/CA2 | bidirectional | General-purpose digital I/O P2.0, or ACLK clock output, or Comparator_A input CA2. |
| 21 | P2.1/TAINCLK/CA3 | bidirectional | General-purpose digital I/O P2.1, or Timer_A INCLK clock input, or Comparator_A input CA3. |
| 22 | P2.2/CAOUT/TA0/CA4 | bidirectional | General-purpose digital I/O P2.2, or Timer_A CCI0B capture input, or Comparator_A output/input CA4, and BSL receive. |
| 23 | P2.3/CA0/TA1 | bidirectional | General-purpose digital I/O P2.3, or Timer_A Out1 output, or Comparator_A input CA0. |
| 24 | P2.4/CA1/TA2 | bidirectional | General-purpose digital I/O P2.4, or Timer_A Out2 output, or Comparator_A input CA1. |
| 25 | P2.5/ROSC/CA5 | bidirectional | General-purpose digital I/O P2.5, or input for the external resistor ROSC that defines the nominal DCO frequency, or Comparator_A input CA5. |
| 26 | P2.6/ADC12CLK/CA6 | bidirectional | General-purpose digital I/O P2.6, or ADC12 conversion clock output, or Comparator_A input CA6. |
| 27 | P2.7/TA0/CA7 | bidirectional | General-purpose digital I/O P2.7, or Timer_A Out0 output, or Comparator_A input CA7. |
| 28 | P3.0/UCB0STE/UCA0CLK | bidirectional | General-purpose digital I/O P3.0, or USCI_B0 slave transmit enable, or USCI_A0 clock input/output. |
| 29 | P3.1/UCB0SIMO/UCB0SDA | bidirectional | General-purpose digital I/O P3.1, or USCI_B0 SPI slave-in/master-out, or I2C data SDA. |
| 30 | P3.2/UCB0SOMI/UCB0SCL | bidirectional | General-purpose digital I/O P3.2, or USCI_B0 SPI slave-out/master-in, or I2C clock SCL; in I2C mode the output drives only logic 0 to VSS. |
| 31 | P3.3/UCB0CLK/UCA0STE | bidirectional | General-purpose digital I/O P3.3, or USCI_B0 clock input/output, or USCI_A0 slave transmit enable. |
| 32 | P3.4/UCA0TXD/UCA0SIMO | bidirectional | General-purpose digital I/O P3.4, or USCI_A0 UART transmit data output, or SPI slave-in/master-out. |
| 33 | P3.5/UCA0RXD/UCA0SOMI | bidirectional | General-purpose digital I/O P3.5, or USCI_A0 UART receive data input, or SPI slave-out/master-in. |
| 34 | P3.6 | bidirectional | General-purpose digital I/O P3.6 with no USCI_A1 alternate function on the MSP430F23x device. |
| 35 | P3.7 | bidirectional | General-purpose digital I/O P3.7 with no USCI_A1 alternate function on the MSP430F23x device. |
| 36 | P4.0/TB0 | bidirectional | General-purpose digital I/O P4.0, or Timer_B CCI0A/CCI0B capture input and Out0 output. |
| 37 | P4.1/TB1 | bidirectional | General-purpose digital I/O P4.1, or Timer_B CCI1A/CCI1B capture input and Out1 output. |
| 38 | P4.2/TB2 | bidirectional | General-purpose digital I/O P4.2, or Timer_B CCI2A/CCI2B capture input and Out2 output. |
| 39 | P4.3 | bidirectional | General-purpose digital I/O P4.3 with no Timer_B alternate function on the MSP430F23x device (Timer_B3 has only three CCRs). |
| 40 | P4.4 | bidirectional | General-purpose digital I/O P4.4 with no Timer_B alternate function on the MSP430F23x device. |
| 41 | P4.5 | bidirectional | General-purpose digital I/O P4.5 with no Timer_B alternate function on the MSP430F23x device. |
| 42 | P4.6 | bidirectional | General-purpose digital I/O P4.6 with no Timer_B alternate function on the MSP430F23x device. |
| 43 | P4.7/TBCLK | bidirectional | General-purpose digital I/O P4.7, or Timer_B TBCLK clock input. |
| 44 | P5.0 | bidirectional | General-purpose digital I/O P5.0 with no USCI_B1/USCI_A1 alternate function on the MSP430F23x device. |
| 45 | P5.1 | bidirectional | General-purpose digital I/O P5.1 with no USCI_B1 alternate function on the MSP430F23x device. |
| 46 | P5.2 | bidirectional | General-purpose digital I/O P5.2 with no USCI_B1 alternate function on the MSP430F23x device. |
| 47 | P5.3 | bidirectional | General-purpose digital I/O P5.3 with no USCI_B1/USCI_A1 alternate function on the MSP430F23x device. |
| 48 | P5.4/MCLK | bidirectional | General-purpose digital I/O P5.4, or MCLK master system clock output. |
| 49 | P5.5/SMCLK | bidirectional | General-purpose digital I/O P5.5, or SMCLK subsystem clock output. |
| 50 | P5.6/ACLK | bidirectional | General-purpose digital I/O P5.6, or ACLK auxiliary clock output. |
| 51 | P5.7/TBOUTH/SVSOUT | bidirectional | General-purpose digital I/O P5.7, or Timer_B TBOUTH (switches all PWM outputs to high impedance), or SVS comparator output. |
| 52 | XT2OUT | output | Output of crystal oscillator XT2. |
| 53 | XT2IN | input | Input to crystal oscillator XT2. |
| 54 | TDO/TDI | bidirectional | JTAG test data output, or programming data input terminal; during fuse blow it is used to apply the test input data. |
| 55 | TDI/TCLK | input | JTAG test data input or test clock input; the device protection fuse is connected to this pin. |
| 56 | TMS | input | JTAG test mode select, used as the input port for device programming and test. |
| 57 | TCK | input | JTAG test clock, the clock input port for device programming, test and bootloader start. |
| 58 | RST/NMI | input | Reset input, non-maskable interrupt input, or bootloader start (in flash devices). |
| 59 | P6.0/A0 | bidirectional | General-purpose digital I/O P6.0, or 12-bit ADC analog input A0. |
| 60 | P6.1/A1 | bidirectional | General-purpose digital I/O P6.1, or 12-bit ADC analog input A1. |
| 61 | P6.2/A2 | bidirectional | General-purpose digital I/O P6.2, or 12-bit ADC analog input A2. |
| 62 | AVSS | power_in | Analog supply voltage, negative terminal; supplies only the analog part of the ADC12. |
| 63 | DVSS | power_in | Digital supply voltage, negative terminal; supplies all digital parts (ground). |
| 64 | AVCC | power_in | Analog supply voltage, positive terminal; supplies only the analog part of the ADC12. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
MSP430F235TPM - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
msp430f235tpm-etched.step/msp430f235tpm-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430f235tpm.step/msp430f235tpm.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (102 pp, sha256
841108068ef96d3c, retrieved 2026-10-10, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).