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MSP430F2132QRHBREP

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Texas Instruments Microcontroller Units (MCUs/MPUs/SOCs), VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSP430F2132QRHBREP

Texas Instruments · Microcontroller Units (MCUs/MPUs/SOCs) · VQFN-32-EP(5x5)

MSP430F2132QRHBREP from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DVSS power_in Digital supply voltage ground pin; the datasheet lists it as the digital supply ground terminal.
2 XOUT/P2.7/CA7 bidirectional Output terminal of the crystal oscillator, also general-purpose I/O P2.7 and Comparator_A+ input CA7.
3 XIN/P2.6/CA6 bidirectional Input terminal of the crystal oscillator, also general-purpose I/O P2.6 and Comparator_A+ input CA6.
4 NC unconnected Not connected internally; connection to VSS is recommended.
5 RST/NMI/SBWTDIO input Reset or nonmaskable interrupt input, also the Spy-Bi-Wire test data input/output during programming and test.
6 P2.0/ACLK/A0/CA2 bidirectional General-purpose digital I/O pin, also ACLK signal output, ADC10 analog input A0 and Comparator_A+ input CA2.
7 P2.1/TAINCLK/SMCLK/A1/CA3 bidirectional General-purpose digital I/O pin, also Timer TAINCLK clock input, SMCLK signal output, ADC10 analog input A1 and Comparator_A+ input CA3.
8 P2.2/TA0.0/A2/CA4/CAOUT bidirectional General-purpose digital I/O pin, also Timer0_A3 CCI0B input and Out0 output, ADC10 analog input A2, Comparator_A+ input CA4 and Comparator_A+ output CAOUT.
9 P3.0/UCB0STE/UCA0CLK/A5 bidirectional General-purpose digital I/O pin, also USCI_B0 slave transmit enable, USCI_A0 clock input/output and ADC10 analog input A5.
10 P3.1/UCB0SIMO/UCB0SDA bidirectional General-purpose digital I/O pin, also USCI_B0 slave in/master out in SPI mode and I2C data SDA in I2C mode.
11 P3.2/UCB0SOMI/UCB0SCL bidirectional General-purpose digital I/O pin, also USCI_B0 slave out/master in in SPI mode and I2C clock SCL in I2C mode.
12 P3.3/UCB0CLK/UCA0STE bidirectional General-purpose digital I/O pin, also USCI_B0 clock input/output and USCI_A0 slave transmit enable.
13 P3.4/UCA0TXD/UCA0SIMO bidirectional General-purpose digital I/O pin, also USCI_A0 transmit data output in UART mode and slave data in/master out in SPI mode.
14 P3.5/UCA0RXD/UCA0SOMI bidirectional General-purpose digital I/O pin, also USCI_A0 receive data input in UART mode and slave data out/master in in SPI mode.
15 P3.6/TA1.0/A6 bidirectional General-purpose digital I/O pin, also Timer1_A2 CCI0B input and Out0 output, and ADC10 analog input A6.
16 P3.7/TA1.1/A7 bidirectional General-purpose digital I/O pin, also Timer1_A2 CCI1A input and Out1 output, and ADC10 analog input A7.
17 NC unconnected Not connected internally; connection to VSS is recommended.
18 P2.3/TA0.1/A3/VREF-/VeREF-/CA0 bidirectional General-purpose digital I/O pin, also Timer0_A3 Out1 output, ADC10 analog input A3 and negative reference VREF-/VeREF-, and Comparator_A+ input CA0.
19 P2.4/TA0.2/A4/VREF+/VeREF+/CA1 bidirectional General-purpose digital I/O pin, also Timer0_A3 Out2 output, ADC10 analog input A4 and positive reference VREF+/VeREF+, and Comparator_A+ input CA1.
20 NC unconnected Not connected internally; connection to VSS is recommended.
21 P1.0/TACLK/ADC10CLK/CAOUT bidirectional General-purpose digital I/O pin, also Timer0_A3 and Timer1_A2 TACLK clock input, ADC10 conversion clock and Comparator_A+ output.
22 P1.1/TA0.0/TA1.0 bidirectional General-purpose digital I/O pin, also Timer0_A3 CCI0A input and Out0 output, and Timer1_A2 CCI0A input.
23 P1.2/TA0.1 bidirectional General-purpose digital I/O pin, also Timer0_A3 CCI1A input and Out1 output.
24 P1.3/TA0.2 bidirectional General-purpose digital I/O pin, also Timer0_A3 CCI2A input and Out2 output.
25 P1.4/SMCLK/TCK bidirectional General-purpose digital I/O pin, also SMCLK signal output and JTAG test clock input TCK for device programming and test.
26 P1.5/TA0.0/TMS bidirectional General-purpose digital I/O pin, also Timer0_A3 Out0 output and JTAG test mode select input TMS for device programming and test.
27 P1.6/TA0.1/TDI/TCLK bidirectional General-purpose digital I/O pin, also Timer0_A3 Out1 output and JTAG test data input or test clock input TDI/TCLK in programming and test.
28 P1.7/TA0.2/TDO/TDI bidirectional General-purpose digital I/O pin, also Timer0_A3 Out2 output and JTAG test data output TDO or test data input TDI in programming and test.
29 TEST/SBWTCK input Selects test mode for the JTAG pins on Port 1; the device protection fuse is connected to this TEST terminal.
30 DVCC power_in Digital supply voltage input; the features list gives the low supply voltage range as 1.8 V to 3.6 V.
31 NC unconnected Not connected internally; connection to VSS is recommended.
32 P2.5/ROSC/CA5 bidirectional General-purpose digital I/O pin, also input for an external resistor defining the DCO nominal frequency (ROSC) and Comparator_A+ input CA5.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(5x5)
Category Single Chip Microcomputer/Microcontroller
Pins 33

CAD (KiCad official)

  • Symbol: MSP430F2132QRHBREP
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: msp430f2132qrhbrep-etched.step / msp430f2132qrhbrep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430f2132qrhbrep.step / msp430f2132qrhbrep.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (73 pp, sha256 9110a1f9039540d8, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF