Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

MSP430F2121IRGER

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-24(4x4)

MSP430F2121IRGER from Texas Instruments, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected Not internally connected.
2 VSS power_in Ground reference.
3 XOUT/P2.7/CA7 bidirectional Output terminal of crystal oscillator, general-purpose digital I/O pin, or Comparator_A+ CA7 input.
4 XIN/P2.6/CA6 bidirectional Input terminal of crystal oscillator, general-purpose digital I/O pin, or Comparator_A+ CA6 input.
5 RST/NMI input Reset or nonmaskable interrupt input.
6 P2.0/ACLK/CA2 bidirectional General-purpose digital I/O pin, ACLK output, or Comparator_A+ CA2 input.
7 P2.1/INCLK/CA3 bidirectional General-purpose digital I/O pin, Timer_A clock signal INCLK input, or Comparator_A+ CA3 input.
8 P2.2/CAOUT/TA0/CA4 bidirectional General-purpose digital I/O pin, Timer_A capture CCI0B input/BSL receive, Comparator_A+ output, or CA4 input.
9 NC unconnected Not internally connected.
10 P2.3/TA1/CA0 bidirectional General-purpose digital I/O pin, Timer_A compare Out1 output, or Comparator_A+ CA0 input.
11 P2.4/TA2/CA1 bidirectional General-purpose digital I/O pin, Timer_A compare Out2 output, or Comparator_A+ CA1 input.
12 NC unconnected Not internally connected.
13 P1.0/TACLK bidirectional General-purpose digital I/O pin or Timer_A clock signal TACLK input.
14 P1.1/TA0 bidirectional General-purpose digital I/O pin, Timer_A capture CCI0A input, compare Out0 output, or BSL transmit.
15 P1.2/TA1 bidirectional General-purpose digital I/O pin, Timer_A capture CCI1A input, or compare Out1 output.
16 P1.3/TA2 bidirectional General-purpose digital I/O pin, Timer_A capture CCI2A input, or compare Out2 output.
17 P1.4/SMCLK/TCK bidirectional General-purpose digital I/O pin, SMCLK signal output, or Test Clock input for device programming and test.
18 P1.5/TA0/TMS bidirectional General-purpose digital I/O pin, Timer_A compare Out0 output, or Test Mode Select input for device programming and test.
19 NC unconnected Not internally connected.
20 P1.6/TA1/TDI/TCLK bidirectional General-purpose digital I/O pin, Timer_A compare Out1 output, or Test Data Input/Test Clock Input for programming and test.
21 P1.7/TA2/TDO/TDI bidirectional General-purpose digital I/O pin, Timer_A compare Out2 output, or Test Data Output/Input for programming and test.
22 TEST input Selects test mode for JTAG pins on Port1; device protection fuse is connected to TEST.
23 VCC power_in Supply voltage.
24 P2.5/CA5 bidirectional General-purpose digital I/O pin or Comparator_A+ CA5 input.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24(4x4)
Category Embedded Processors & Controllers
Pins 25

CAD (KiCad official)

  • Symbol: MSP430F2121IRGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: msp430f2121irger-etched.step / msp430f2121irger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430f2121irger.step / msp430f2121irger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (68 pp, sha256 0997b19db742fa9b, retrieved 2026-10-01, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF