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MSP430AFE232IPW
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+61@@ -0,0 +1,61 @@+# MSP430AFE232IPW++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · TSSOP-24++MSP430AFE232IPW from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A0.0+ | input | SD24_A positive analog input A0.0. |+| 2 | A0.0- | input | SD24_A negative analog input A0.0. |+| 3 | A1.0+ | input | SD24_A positive analog input A1.0 (present on MSP430AFE2x2; not available on MSP430AFE2x1). |+| 4 | A1.0- | input | SD24_A negative analog input A1.0 (present on MSP430AFE2x2; not available on MSP430AFE2x1). |+| 5 | AVCC | power_in | Analog supply voltage, positive terminal; must not power up prior to DVCC. |+| 6 | AVSS | power_in | Analog supply voltage, negative terminal. |+| 7 | VREF | power_in | Input for an external reference voltage, or output for the internal reference voltage (can be used as mid-voltage). |+| 8 | NC | unconnected | No internal connection on the AFE2x2 variant; the datasheet says to connect NC pins to analog ground (AVSS). |+| 9 | NC | unconnected | No internal connection on the AFE2x2 variant; the datasheet says to connect NC pins to analog ground (AVSS). |+| 10 | TEST/SBWTCK | input | Selects test mode for the JTAG pins P1.5 to P1.7 and P2.0; the device protection fuse is connected to TEST, and it serves as the Spy-Bi-Wire test clock input. |+| 11 | RST/NMI/SBWTDIO | input | Reset or nonmaskable interrupt input; also the Spy-Bi-Wire test data input/output for device programming and test. |+| 12 | P1.0/SVSIN/TACLK/SMCLK/TA2 | bidirectional | General-purpose digital I/O; also analog input to the supply voltage supervisor, Timer_A3 TACLK input, SMCLK output, and Timer_A3 compare Out2. |+| 13 | DVSS | power_in | Digital supply voltage, negative terminal. |+| 14 | P2.6/XT2IN | bidirectional | Input terminal of the crystal oscillator; also a general-purpose digital I/O pin. |+| 15 | P2.7/XT2OUT | bidirectional | Output terminal of the crystal oscillator; also a general-purpose digital I/O pin. |+| 16 | DVCC | power_in | Digital supply voltage, positive terminal. |+| 17 | P1.1/TA1/SDCLK | bidirectional | General-purpose digital I/O; also Timer_A3 capture inputs CCI1A/CCI1B, compare Out1 output, and SD24_A bit-stream clock output. |+| 18 | P1.2/TA0/SD0DO | bidirectional | General-purpose digital I/O; also Timer_A3 capture inputs CCI0A/CCI0B, compare Out0 output, and SD24_A bit-stream data output for channel 0. |+| 19 | P1.3/UTXD0/SD1DO | bidirectional | General-purpose digital I/O; also USART0 UART transmit data out and SD24_A bit-stream data output for channel 1. |+| 20 | P1.4/URXD0 | bidirectional | General-purpose digital I/O; also USART0 UART receive data input (SD2DO is not available on the AFE2x2 variant). |+| 21 | P1.5/SIMO0/SVSOUT/TMS | bidirectional | General-purpose digital I/O; also USART0 SPI slave-in/master-out, SVS comparator output, and JTAG test mode select (TMS input for programming and test). |+| 22 | P1.6/SOMI0/TA2/TCK | bidirectional | General-purpose digital I/O; also USART0 SPI slave-out/master-in, Timer_A3 compare Out2 output, and JTAG test clock (TCK input for programming and test). |+| 23 | P1.7/UCLK0/TA1/TDO/TDI | bidirectional | General-purpose digital I/O; also USART0 external clock input/output in UART or SPI mode, Timer_A3 compare Out1 output, and JTAG TDO/TDI data output or programming data input. |+| 24 | P2.0/STE0/TA0/TDI/TCLK | bidirectional | General-purpose digital I/O; also USART0 SPI slave transmit enable, Timer_A3 compare Out0 output, and JTAG TDI or test clock input for programming and test. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-24 |+| Category | Embedded Processors & Controllers |+| Pins | 24 |++## CAD (KiCad official)++- Symbol: `MSP430AFE232IPW`+- Footprint: `Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm`+- 3D model: TSSOP-24 (KiCad packages3D, STEP)+- 3D model files: `msp430afe232ipw-etched.step` / `msp430afe232ipw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430afe232ipw.step` / `msp430afe232ipw.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430afe232) (63 pp, sha256 `2b9d6953a48a5335`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/msp430afe232ipw-datasheet.pdf)
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not available on MSP430AFE2x1)."+ },+ {+ "number": "4",+ "name": "A1.0-",+ "type": "input",+ "description": "SD24_A negative analog input A1.0 (present on MSP430AFE2x2; not available on MSP430AFE2x1)."+ },+ {+ "number": "5",+ "name": "AVCC",+ "type": "power_in",+ "description": "Analog supply voltage, positive terminal; must not power up prior to DVCC."+ },+ {+ "number": "6",+ "name": "AVSS",+ "type": "power_in",+ "description": "Analog supply voltage, negative terminal."+ },+ {+ "number": "7",+ "name": "VREF",+ "type": "power_in",+ "description": "Input for an external reference voltage, or output for the internal reference voltage (can be used as mid-voltage)."+ },+ {+ "number": "8",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection on the AFE2x2 variant; the datasheet says to connect NC pins to analog ground (AVSS)."+ },+ {+ "number": "9",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection on the AFE2x2 variant; the datasheet says to connect NC pins to analog ground (AVSS)."+ },+ {+ "number": "10",+ "name": "TEST/SBWTCK",+ "type": "input",+ "description": "Selects test mode for the JTAG pins P1.5 to P1.7 and P2.0; the device protection fuse is connected to TEST, and it serves as the Spy-Bi-Wire test clock input."+ },+ {+ "number": "11",+ "name": "RST/NMI/SBWTDIO",+ "type": "input",+ "description": "Reset or nonmaskable interrupt input; also the Spy-Bi-Wire test data input/output for device programming and test."+ },+ {+ "number": "12",+ "name": "P1.0/SVSIN/TACLK/SMCLK/TA2",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; also analog input to the supply voltage supervisor, Timer_A3 TACLK input, SMCLK output, and Timer_A3 compare Out2."+ },+ {+ "number": "13",+ "name": "DVSS",+ "type": "power_in",+ "description": "Digital supply voltage, negative terminal."+ },+ {+ "number": "14",+ "name": "P2.6/XT2IN",+ "type": "bidirectional",+ "description": "Input terminal of the crystal oscillator; also a general-purpose digital I/O pin."+ },+ {+ "number": "15",+ "name": "P2.7/XT2OUT",+ "type": "bidirectional",+ "description": "Output terminal of the crystal oscillator; also a general-purpose digital I/O pin."+ },+ {+ "number": "16",+ "name": "DVCC",+ "type": "power_in",+ "description": "Digital supply voltage, positive terminal."+ },+ {+ "number": "17",+ "name": "P1.1/TA1/SDCLK",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; also Timer_A3 capture inputs CCI1A/CCI1B, compare Out1 output, and SD24_A bit-stream clock output."+ },+ {+ "number": "18",+ "name": "P1.2/TA0/SD0DO",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; also Timer_A3 capture inputs CCI0A/CCI0B, compare Out0 output, and SD24_A bit-stream data output for channel 0."+ },+ {+ "number": "19",+ "name": "P1.3/UTXD0/SD1DO",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; also USART0 UART transmit data out and SD24_A bit-stream data output for channel 1."+ },+ {+ "number": "20",+ "name": "P1.4/URXD0",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; also USART0 UART receive data input (SD2DO is not available on the AFE2x2 variant)."+ },+ {+ "number": "21",+ "name": "P1.5/SIMO0/SVSOUT/TMS",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; also USART0 SPI slave-in/master-out, SVS comparator output, and JTAG test mode select (TMS input for programming and test)."+ },+ {+ "number": "22",+ "name": "P1.6/SOMI0/TA2/TCK",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; also USART0 SPI slave-out/master-in, Timer_A3 compare Out2 output, and JTAG test clock (TCK input for programming and test)."+ },+ {+ "number": "23",+ "name": "P1.7/UCLK0/TA1/TDO/TDI",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; also USART0 external clock input/output in UART or SPI mode, Timer_A3 compare Out1 output, and JTAG TDO/TDI data output or programming data input."+ },+ {+ "number": "24",+ "name": "P2.0/STE0/TA0/TDI/TCLK",+ "type": "bidirectional",+ "description": "General-purpose digital I/O; also USART0 SPI slave transmit enable, Timer_A3 compare Out0 output, and JTAG TDI or test clock input for programming and test."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pins 8 and 9 are NC on the MSP430AFE2x2 variant, which the MSP430AFE232 belongs to. The datasheet sa; Types for TEST/SBWTCK and RST/NMI/SBWTDIO are listed as I in Table 4-1, but they carry bidirectional; The provided text is only 27 of 63 pages. The pinout figure for MSP430AFE2x2 (page 6) and the termin"+ ],+ "pages_sent": 27,+ "cost_usd": 0.1615,+ "at": "2026-10-08T04:36:02"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/msp430afe232",+ "pages": 63,+ "sha256": "2b9d6953a48a5335",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 24,+ "described": 24,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "msp430afe232ipw.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 7.8,+ 0.97+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "706322f42d9793ebf28d5b80100a68bfa8769998a00b78acadf7af937fc1454f",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "msp430afe232ipw-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 7.8,+ 0.97+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "47a5d26c7e63bc6c1052e98c3122a27ddbad314e1af58d4db59659d076e11c73",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}