# MSN4688

**MASPOWER** · MOSFETs · SOP-8

MSN4688 from MASPOWER, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of MOSFET Q1 (pin 1 on the page 1 schematic), tied to the Q1 body diode. |
| 2 | G1 | input | Gate of MOSFET Q1; gate-to-source voltage limit is ±25 V. |
| 3 | S2 | passive | Source of MOSFET Q2 (pin 3 on the page 1 schematic), tied to the Q2 body diode. |
| 4 | G2 | input | Gate of MOSFET Q2; gate-to-source voltage limit is ±25 V. |
| 5 | D2 | passive | Drain of MOSFET Q2, shorted to pin 6 (drain-to-source rating 60 V N-Ch / -45 V P-Ch, depending on the channel). |
| 6 | D2 | passive | Drain of MOSFET Q2, shorted to pin 5 (drain-to-source rating 60 V N-Ch / -45 V P-Ch, depending on the channel). |
| 7 | D1 | passive | Drain of MOSFET Q1, shorted to pin 8 (drain-to-source rating 60 V N-Ch / -45 V P-Ch, depending on the channel). |
| 8 | D1 | passive | Drain of MOSFET Q1, shorted to pin 7 (drain-to-source rating 60 V N-Ch / -45 V P-Ch, depending on the channel). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | MASPOWER |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-to-Source Voltage (N-Ch) | VDSS |  |  | 60 | V |  | 1 |
| Drain-to-Source Voltage (P-Ch) | VDSS |  |  | -45 | V |  | 1 |
| Gate-to-Source Voltage (N-Ch) | VGSS | -25 |  | 25 | V |  | 1 |
| Gate-to-Source Voltage (P-Ch) | VGSS | -25 |  | 25 | V |  | 1 |
| Drain Current DC (N-Ch) | ID |  |  | 5 | A |  | 1 |
| Drain Current DC (P-Ch) | ID |  |  | -3.5 | A |  | 1 |
| Drain Current Pulse (N-Ch) | IDP |  |  | 20 | A | PW ≤ 10μS, duty cycle ≤ 1 | 1 |
| Drain Current Pulse (P-Ch) | IDP |  |  | -14 | A | PW ≤ 10μS, duty cycle ≤ 1 | 1 |
| Allowable Power Dissipation | PD |  |  | 1.3 | W | Mounted on a ceramic board (1000mm2 ×0.8mm) 1unit | 1 |
| Total Dissipation | PT |  |  | 1.7 | W | Mounted on a ceramic board (1000mm2 ×0.8mm) | 1 |
| Channel Temperature (Maximum Junction Temperature) | Tch |  |  | 150 | ℃ |  | 1 |
| Storage Temperature Range | Tstg | -55 |  | 150 | ℃ |  | 1 |
| Drain-to-Source Breakdown Voltage (N-Ch) | V(BR)DSS | 60 |  |  | V | ID = 250μA, VGS = 0V | 1 |
| Drain-to-Source Breakdown Voltage (P-Ch) | V(BR)DSS | -45 |  |  | V | ID = -250μA, VGS = 0V | 1 |
| Zero-Gate Voltage Drain Current (N-Ch) | IDSS |  |  | 1 | μA | VDS = 48V, VGS = 0V | 1 |
| Zero-Gate Voltage Drain Current (P-Ch) | IDSS |  |  | -1 | μA | VDS = -36V, VGS = 0V | 1 |
| Gate-to-Source Leakage Current (N-Ch) | IGSS | -100 |  | 100 | nA | VGS = +25V, VDS = 0V | 1 |
| Gate-to-Source Leakage Current (P-Ch) | IGSS | -100 |  | 100 | nA | VGS = +25V, VDS = 0V | 1 |
| Gate Threshold Voltage (N-Ch) | VGS(th) | 1 | 2 | 2.5 | V | VDS = VGS, ID = 250μA | 2 |
| Gate Threshold Voltage (P-Ch) | VGS(th) | -1 | -2 | -2.5 | V | VDS = VGS, ID = -250μA | 2 |
| Static Drain-to-Source On-State Resistance (N-Ch) | RDS(ON) |  |  | 100 | mΩ | ID = 5A, VGS = 10V | 2 |
| Static Drain-to-Source On-State Resistance (P-Ch) | RDS(ON) |  | 80 | 100 | mΩ | ID = -3.5A, VGS = -10 | 2 |
| Static Drain-to-Source On-State Resistance (N-Ch) | RDS(ON) |  | 55 | 75 | mΩ | ID = 4A, VGS = 4.5V | 2 |
| Static Drain-to-Source On-State Resistance (P-Ch) | RDS(ON) |  | 100 | 135 | mΩ | ID = -3.1A, VGS = -4.5 | 2 |
| Turn-on Delay Time (N-Ch) | td(on) |  | 9 | 17 | nS | VGEN = 10V, VDS = 30V, RL = 30Ω, ID = 1A, RGEN = 6Ω | 2 |
| Turn-on Delay Time (P-Ch) | td(on) |  | 7 | 14 | nS | VGEN = -10V, VDS = -22.5V, RL = 30Ω, ID = -1A, RGEN = 6Ω | 2 |
| Rise Time (N-Ch) | tr |  | 6 | 12 | nS | VGEN = 10V, VDS = 30V, RL = 30Ω, ID = 1A, RGEN = 6Ω | 2 |
| Rise Time (P-Ch) | tr |  | 8 | 15 | nS | VGEN = -10V, VDS = -22.5V, RL = 30Ω, ID = -1A, RGEN = 6Ω | 2 |
| Turn-off Delay Time (N-Ch) | td(off) |  | 25 | 46 | nS | VGEN = 10V, VDS = 30V, RL = 30Ω, ID = 1A, RGEN = 6Ω | 2 |
| Turn-off Delay Time (P-Ch) | td(off) |  | 47 | 86 | nS | VGEN = -10V, VDS = -22.5V, RL = 30Ω, ID = -1A, RGEN = 6Ω | 2 |
| Fall Time (N-Ch) | tf |  | 5 | 10 | nS | VGEN = 10V, VDS = 30V, RL = 30Ω, ID = 1A, RGEN = 6Ω | 2 |
| Fall Time (P-Ch) | tf |  | 17 | 32 | nS | VGEN = -10V, VDS = -22.5V, RL = 30Ω, ID = -1A, RGEN = 6Ω | 2 |
| Total Gate Charge (N-Ch) | Qg |  | 19 | 27 | nC | VDS = 30V, VGS = 10V, ID = 5A | 2 |
| Total Gate Charge (P-Ch) | Qg |  | 22 | 31 | nC | VDS = -22.5V, VGS = -10V | 2 |
| Diode Forward Voltage (N-Ch) | VSD |  | 0.8 | 1.1 | V | IS = 2.5A, VGS = 0 | 3 |
| Diode Forward Voltage (P-Ch) | VSD |  | -0.8 | -1.1 | V | IS = -2.5A, VGS = 0 | 3 |

## CAD (KiCad official)

- Symbol: `MSN4688`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `msn4688-etched.step` / `msn4688-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msn4688.step` / `msn4688.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [MASPOWER datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590903773843828736) (7 pp, sha256 `94a7b05b14fb34a0`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/msn4688-datasheet.pdf)