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MSC1210Y3PAGR

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Texas Instruments Analog To Digital Converters (ADC), TQFP-64(10x10). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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MSC1210Y3PAGR

Texas Instruments · Analog To Digital Converters (ADC) · TQFP-64(10x10)

MSC1210Y3PAGR from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 XOUT output Crystal oscillator output supporting AT cut fundamentalfrequency crystals (1-18 MHz) or ceramic resonators (1-16 MHz).
2 XIN input Crystal oscillator input supporting AT cut crystals or ceramic resonators, can also be external clock input (0-33 MHz).
3 P3.0/RxD0 bidirectional Port 3 bit 0 bidirectional I/O with alternate function Serial port 0 receive input.
4 P3.1/TxD0 bidirectional Port 3 bit 1 bidirectional I/O with alternate function Serial port 0 transmit output.
5 P3.2/INT0 bidirectional Port 3 bit 2 bidirectional I/O with alternate function External interrupt 0 input.
6 P3.3/INT1/TONE/PWM bidirectional Port 3 bit 3 bidirectional I/O with alternate functions External interrupt 1, TONE output, or PWM output.
7 P3.4/T0 bidirectional Port 3 bit 4 bidirectional I/O with alternate function Timer 0 external counter input.
8 P3.5/T1 bidirectional Port 3 bit 5 bidirectional I/O with alternate function Timer 1 external counter input.
9 P3.6/WR bidirectional Port 3 bit 6 bidirectional I/O with alternate function external data memory write strobe.
10 P3.7/RD bidirectional Port 3 bit 7 bidirectional I/O with alternate function external data memory read strobe.
11 DVDD power_in Digital power supply, requires 2.7 V to 5.25 V for device operation.
12 DGND power_in Digital ground reference for digital power supply.
13 RST input Reset input, HIGH for two tOSC periods resets the device.
14 DVDD power_in Digital power supply, requires 2.7 V to 5.25 V for device operation.
15 DVDD power_in Digital power supply, requires 2.7 V to 5.25 V for device operation.
16 NC unconnected No connection, must be left unconnected to avoid device damage.
17 AGND power_in Analog ground reference for analog power supply.
18 AIN0 input Analog input channel 0, accepts differential or single-ended signals in range AGND−0.1 V to AVDD+0.1 V (buffer OFF) or AGND+50 mV to AVDD−1.5 V (buffer ON).
19 AIN1 input Analog input channel 1, accepts differential or single-ended signals in range AGND−0.1 V to AVDD+0.1 V (buffer OFF) or AGND+50 mV to AVDD−1.5 V (buffer ON).
20 AIN2 input Analog input channel 2, accepts differential or single-ended signals in range AGND−0.1 V to AVDD+0.1 V (buffer OFF) or AGND+50 mV to AVDD−1.5 V (buffer ON).
21 AIN3 input Analog input channel 3, accepts differential or single-ended signals in range AGND−0.1 V to AVDD+0.1 V (buffer OFF) or AGND+50 mV to AVDD−1.5 V (buffer ON).
22 AIN4 input Analog input channel 4, accepts differential or single-ended signals in range AGND−0.1 V to AVDD+0.1 V (buffer OFF) or AGND+50 mV to AVDD−1.5 V (buffer ON).
23 AIN5 input Analog input channel 5, accepts differential or single-ended signals in range AGND−0.1 V to AVDD+0.1 V (buffer OFF) or AGND+50 mV to AVDD−1.5 V (buffer ON).
24 AIN6/EXTD input Analog input channel 6 with digital low-voltage detect input, accepts signals with digital level 0.2·DVDD to DVDD, generates DLVD interrupt on low voltage condition.
25 AIN7/EXTA input Analog input channel 7 with analog low-voltage detect input, accepts differential or single-ended signals, generates ALVD interrupt on low voltage condition.
26 AINCOM input Analog common for single-ended inputs or negative input for differential measurements, input range AGND−0.1 V to AVDD+0.1 V.
27 AGND power_in Analog ground reference for analog power supply.
28 AVDD power_in Analog power supply, requires 4.75 V to 5.25 V (for internal VREF at 2.5 V) or 2.7 V to 3.6 V (for internal VREF at 1.25 V).
29 REF IN− input Voltage reference negative input, input range AGND to AVDD, must be tied to AGND when using internal VREF.
30 REF IN+ input Voltage reference positive input, accepts external reference in range AGND to AVDD or 0.1 V to 2.5 V (AVDD=5V) or 0.1 V to 1.25 V (AVDD=3V).
31 REF OUT output Internal voltage reference output, 2.495 V to 2.505 V at 25 °C (VREFH=1, AVDD=5V) or 1.245 V to 1.255 V (VREFH=0, AVDD=3V), tie to REF IN+ for internal VREF with 0.1 µF capacitor to AGND.
32 NC unconnected No connection, must be left unconnected to avoid device damage.
33 NC unconnected No connection, must be left unconnected to avoid device damage.
34 P2.0/A8 bidirectional Port 2 bit 0 bidirectional I/O with alternate function Address bit 8 for external memory access.
35 P2.1/A9 bidirectional Port 2 bit 1 bidirectional I/O with alternate function Address bit 9 for external memory access.
36 P2.2/A10 bidirectional Port 2 bit 2 bidirectional I/O with alternate function Address bit 10 for external memory access.
37 P2.3/A11 bidirectional Port 2 bit 3 bidirectional I/O with alternate function Address bit 11 for external memory access.
38 P2.4/A12 bidirectional Port 2 bit 4 bidirectional I/O with alternate function Address bit 12 for external memory access.
39 P2.5/A13 bidirectional Port 2 bit 5 bidirectional I/O with alternate function Address bit 13 for external memory access.
40 P2.6/A14 bidirectional Port 2 bit 6 bidirectional I/O with alternate function Address bit 14 for external memory access.
41 DGND power_in Digital ground reference for digital power supply.
42 DVDD power_in Digital power supply, requires 2.7 V to 5.25 V for device operation.
43 P2.7/A15 bidirectional Port 2 bit 7 bidirectional I/O with alternate function Address bit 15 for external memory access.
44 PSEN/OSCCLK/MODCLK output Program store enable (active low chip enable for external memory), or oscillator clock, modulator clock, HIGH, or LOW output selectable via PASEL register configuration.
45 ALE output Address Latch Enable for latching low byte of address during external memory access, emitted at 1/4 oscillator frequency or HIGH/LOW selectable via PASEL register configuration.
46 P0.0/AD0 bidirectional Port 0 bit 0 bidirectional I/O with alternate multiplexed Address/Data bit 0 function for external memory access.
47 P0.1/AD1 bidirectional Port 0 bit 1 bidirectional I/O with alternate multiplexed Address/Data bit 1 function for external memory access.
48 EA input External Access Enable, must be held LOW at end of RESET to fetch program from external memory starting at 0000h, no internal pull-up.
49 P0.2/AD2 bidirectional Port 0 bit 2 bidirectional I/O with alternate multiplexed Address/Data bit 2 function for external memory access.
50 P0.3/AD3 bidirectional Port 0 bit 3 bidirectional I/O with alternate multiplexed Address/Data bit 3 function for external memory access.
51 P0.4/AD4 bidirectional Port 0 bit 4 bidirectional I/O with alternate multiplexed Address/Data bit 4 function for external memory access.
52 P0.5/AD5 bidirectional Port 0 bit 5 bidirectional I/O with alternate multiplexed Address/Data bit 5 function for external memory access.
53 P0.6/AD6 bidirectional Port 0 bit 6 bidirectional I/O with alternate multiplexed Address/Data bit 6 function for external memory access.
54 P0.7/AD7 bidirectional Port 0 bit 7 bidirectional I/O with alternate multiplexed Address/Data bit 7 function for external memory access.
55 P1.0/T2 bidirectional Port 1 bit 0 bidirectional I/O with alternate function Timer 2 external counter input.
56 P1.1/T2EX bidirectional Port 1 bit 1 bidirectional I/O with alternate function Timer 2 capture/reload trigger external input.
57 DGND power_in Digital ground reference for digital power supply.
58 DVDD power_in Digital power supply, requires 2.7 V to 5.25 V for device operation.
59 P1.2/RxD1 bidirectional Port 1 bit 2 bidirectional I/O with alternate function Serial port 1 receive input.
60 P1.3/TxD1 bidirectional Port 1 bit 3 bidirectional I/O with alternate function Serial port 1 transmit output.
61 P1.4/INT2/SS bidirectional Port 1 bit 4 bidirectional I/O with alternate functions External interrupt 2 or SPI slave select.
62 P1.5/INT3/MOSI bidirectional Port 1 bit 5 bidirectional I/O with alternate functions External interrupt 3 or SPI Master Out−Slave In.
63 P1.6/INT4/MISO bidirectional Port 1 bit 6 bidirectional I/O with alternate functions External interrupt 4 or SPI Master In−Slave Out.
64 P1.7/INT5/SCLK bidirectional Port 1 bit 7 bidirectional I/O with alternate functions External interrupt 5 or SPI serial clock.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-64(10x10)
Category Data Acquisition
Pins 64

CAD (KiCad official)

  • Symbol: MSC1210Y3PAGR
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: msc1210y3pagr-etched.step / msc1210y3pagr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msc1210y3pagr.step / msc1210y3pagr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (96 pp, sha256 df423689a65a20fc, retrieved 2026-09-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF