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MS9280
Public Made by Adomby adom
Hangzhou Ruimeng Tech Analog To Digital Converters (ADC), SSOP-28-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMS9280
Hangzhou Ruimeng Tech · Analog To Digital Converters (ADC) · SSOP-28-208mil
MS9280 from Hangzhou Ruimeng Tech, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AVSS | power_in | Analog ground for the ADC core, to which AIN and the reference network are referenced (absolute maximum AVSS to AVDD is -0.3 V to +6.5 V). |
| 2 | DRVDD | power_in | Digital output driver supply, specified at 2.7 V to 5.5 V (3 V typical), with absolute maximum DRVDD to DRVSS of -0.3 V to +6.5 V. |
| 3 | D0 | tri_state | Digital output bit 0, the least significant bit of the binary output; high-impedance when THREE_STATE is high. |
| 4 | D1 | tri_state | Digital output bit 1 of the 10-bit binary output; high-impedance when THREE_STATE is high. |
| 5 | D2 | tri_state | Digital output bit 2 of the 10-bit binary output; high-impedance when THREE_STATE is high. |
| 6 | D3 | tri_state | Digital output bit 3 of the 10-bit binary output; high-impedance when THREE_STATE is high. |
| 7 | D4 | tri_state | Digital output bit 4 of the 10-bit binary output; high-impedance when THREE_STATE is high. |
| 8 | D5 | tri_state | Digital output bit 5 of the 10-bit binary output; high-impedance when THREE_STATE is high. |
| 9 | D6 | tri_state | Digital output bit 6 of the 10-bit binary output; high-impedance when THREE_STATE is high. |
| 10 | D7 | tri_state | Digital output bit 7 of the 10-bit binary output; high-impedance when THREE_STATE is high. |
| 11 | D8 | tri_state | Digital output bit 8 of the 10-bit binary output; high-impedance when THREE_STATE is high. |
| 12 | D9 | tri_state | Digital output bit 9, the most significant bit of the binary output; high-impedance when THREE_STATE is high. |
| 13 | OTR | output | Out-of-range flag that indicates the input has exceeded the minimum or maximum quantization range. |
| 14 | DRVSS | power_in | Digital ground for the output drivers, with DRVSS to AVSS limited to -0.3 V to +0.3 V. |
| 15 | CLK | input | Conversion clock input referenced to AVSS with a threshold of AVDD/2; maximum rate 35 MHz with minimum high and low pulse widths of 10 ns. |
| 16 | THREE_STATE | input | Output three-state control: logic high places D0-D9 in high impedance, logic low gives normal operation. |
| 17 | STBY | input | Standby control: logic high puts the device in standby (sleep) mode, logic low selects normal operation; the device returns to normal mode about 400 ns after STBY goes low. |
| 18 | REFSENSE | input | Reference mode select input that chooses between the internal 1 V/2 V reference configurations and external reference operation (see Table 1 and Figures 2d-2g). |
| 19 | CLAMP | input | Clamp control: logic high enables clamp mode, logic low selects non-clamp mode; the clamp is active while CLAMP is high. |
| 20 | CLAMPIN | input | Clamp voltage input that sets the DC level the AIN input is clamped to; the recommended range is 0.5 V to 2.5 V. |
| 21 | REFTS | passive | High reference voltage (top reference) for the ADC, with a range of 1 V to AVDD. |
| 22 | REFTF | passive | High reference decoupling pin, requiring the decoupling network shown in Figure 3 (10 µF and 0.1 µF capacitors). |
| 23 | MODE | input | Mode select input that sets the input range and top/bottom, middle or differential reference configuration (see Table 1); it is tied to AVDD in the main operating mode. |
| 24 | REFBF | passive | Low reference decoupling pin, requiring the decoupling network shown in Figure 3 (10 µF and 0.1 µF capacitors). |
| 25 | REFBS | passive | Low reference voltage (bottom reference) for the ADC, with a range of AVSS (GND) to AVDD-1 V. |
| 26 | VREF | power_in | Internal reference voltage output, nominally 1 V or 2 V depending on the REFSENSE configuration, with a 1.0 µF decoupling capacitor. |
| 27 | AIN | input | Analog signal input, with an input voltage range of REFBS to REFTS and absolute limits of AVSS - 0.3 V to AVDD + 0.3 V. |
| 28 | AVDD | power_in | Analog supply, specified at 2.7 V to 5.5 V (3 V typical), with absolute maximum AVSS to AVDD of -0.3 V to +6.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Hangzhou Ruimeng Tech |
| Package | SSOP-28-208mil |
| Category | Data Acquisition |
| Pins | 28 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 模拟电源电压 Analog supply voltage (rel. AVSS) | AVDD | -0.3 | 6.5 | V | relative to AVSS | 5 | |
| 模拟电源电压 Analog supply voltage (rel. DRVDD) | AVDD | -6.5 | 6.5 | V | relative to DRVDD | 5 | |
| 数字电源电压 Digital supply voltage | DRVDD | -0.3 | 6.5 | V | relative to DRVSS | 5 | |
| 模拟地 Analog ground offset | AVSS | -0.3 | 0.3 | V | relative to DRVSS | 5 | |
| 模式选择引脚电压 MODE pin voltage | MODE | -0.3 | V | relative to AVSS; upper limit AVDD + 0.3 V (not numeric) | 5 | ||
| 时钟输入引脚电压 CLK pin voltage | CLK | -0.3 | V | relative to AVSS; upper limit AVDD + 0.3 V (not numeric) | 5 | ||
| 数字输出电压 Digital output voltage | -0.3 | V | relative to DRVSS; upper limit DRVDD + 0.3 V (not numeric) | 5 | |||
| 模拟输入电压 Analog input voltage | AIN | -0.3 | V | relative to AVSS; upper limit AVDD + 0.3 V (not numeric) | 5 | ||
| 内部基准电压 Internal reference voltage | VREF | -0.3 | V | relative to AVSS; upper limit AVDD + 0.3 V (not numeric) | 5 | ||
| 基准模式选择引脚电压 REFSENSE pin voltage | REFSENSE | -0.3 | V | relative to AVSS; upper limit AVDD + 0.3 V (not numeric) | 5 | ||
| 高电压基准去耦，低电压基准去耦 REFTF/REFBF decoupling pin voltage | REFTF, REFBF | -0.3 | V | relative to AVSS; upper limit AVDD + 0.3 V (not numeric) | 5 | ||
| 高电压基准，低电压基准 REFTS/REFBS reference pin voltage | REFTS, REFBS | -0.3 | V | relative to AVSS; upper limit AVDD + 0.3 V (not numeric) | 5 | ||
| 结温 Junction temperature | 150 | °C | 5 | ||||
| 存储温度 Storage temperature | -65 | 150 | °C | 5 | |||
| 引脚温度 Lead temperature | 300 | °C | 10 s | 5 | |||
| 模拟电源电压 AVDD supply | AVDD | 2.7 | 3 | 5.5 | V | 6 | |
| 数字驱动电压 DRVDD supply | DRVDD | 2.7 | 3 | 5.5 | V | 6 | |
| 工业温度范围 Operating temperature | -40 | 125 | °C | industrial range per product description | 1 | ||
| 微分非线性 Differential nonlinearity | DNL | 0.2 | 1 | LSB | 6 | ||
| 积分非线性 Integral nonlinearity | INL | 0.3 | 1.5 | LSB | 6 | ||
| 失调误差 Offset error | EZS | 0.2 | 1.8 | %FSR | 6 | ||
| 增益误差 Gain error | EFS | 1.2 | 3.9 | %FSR | 6 | ||
| 基准冗差 Reference tolerance | 10 | 25 | mV | 6 | |||
| 高电压基准 REFTS high reference | REFTS | 1 | V | 6 | |||
| VREF (1V) | VREF | 1 | V | 6 | |||
| VREF (2V) | VREF | 2 | V | 6 | |||
| 差分基准 Differential reference | 2 | V | 6 | ||||
| 负载调整 Load regulation (1V) | 0.5 | 2 | mV | 6 | |||
| 输入电容 Input capacitance | CIN | 1 | pF | 6 | |||
| 孔径延迟 Aperture delay | tAD | 4 | ns | 6 | |||
| 孔径抖动 Aperture jitter | tAJ | 2 | ps | 6 | |||
| 输入带宽 Input bandwidth | BW | 300 | MHz | 6 | |||
| DC 漏电流 DC leakage current | 43 | μA | 6 | ||||
| 供电电流 Supply current | IAVDD | 31.7 | 36.7 | mA | 6 | ||
| 功耗 Power dissipation | PD | 95 | 110 | mW | 6 | ||
| 睡眠模式 Sleep mode power | 4 | mW | 6 | ||||
| 信噪比 Signal-to-noise ratio | SNR | 47.8 | 49 | dB | 6 | ||
| 信噪谐波失真比 SINAD | SINAD | 46.5 | 49 | dB | 6 | ||
| 有效位数 ENOB | 7.7 | 7.8 | dB | 7 | |||
| 总谐波失真 Total harmonic distortion | THD | -62 | -49.5 | dB | 7 | ||
| 无杂散动态范围 Spurious-free dynamic range | SFDR | 51.4 | 66 | dB | 7 | ||
| 微分相位 Differential phase | DP | 0.2 | Degree | 7 | |||
| 微分增益 Differential gain | DG | 0.08 | % | 7 | |||
| 输入高电平 Input high voltage | VIH | 2.4 | V | 7 | |||
| 输入低电平 Input low voltage | VIL | 0.3 | V | 7 | |||
| 输出高阻态漏电流 Output high-Z current | IOZ | -10 | 10 | μA | 7 | ||
| 数据有效延迟 Data valid delay | tOD | 25 | ns | 7 | |||
| 数据使能延迟 Data enable delay | tDEN | 25 | ns | 7 | |||
| 数据高阻延迟 Data high-Z delay | tDHZ | 13 | ns | 7 | |||
| 数字输出高电平 Digital output high voltage | VOH | 2.95 | V | Io=50μA | 7 | ||
| 数字输出高电平 Digital output high voltage | VOH | 2.8 | V | Io=500μA | 7 | ||
| 数字输出低电平 Digital output low voltage | VOL | 0.4 | V | Io=1.6mA | 7 | ||
| 数字输出低电平 Digital output low voltage | VOL | 0.05 | V | Io=50μA | 7 | ||
| 时钟高电平脉宽 Clock high pulse width | tCH | 10 | ns | 7 | |||
| 时钟低电平脉宽 Clock low pulse width | tCL | 10 | ns | 7 | |||
| 流水线延迟 Pipeline delay | 3 | Cycles | 7 | ||||
| 钳位误差电压 Clamp error voltage | EOC | 50 | 80 | mV | 7 | ||
| 钳位脉宽 Clamp pulse width | tCPW | 2 | μs | 7 |
CAD (KiCad official)
- Symbol:
MS9280 - Footprint:
Package_SO:SSOP-28_5.3x10.2mm_P0.65mm - 3D model: SSOP-28-208mil (KiCad packages3D, STEP)
- 3D model files:
ms9280-etched.step/ms9280-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ms9280.step/ms9280.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Hangzhou Ruimeng Tech datasheet (24 pp, sha256
c4e2a8e43f4e94dc, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).