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MS8844
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Hangzhou Ruimeng Tech Gate Drive ICs, HTSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MS8844
Hangzhou Ruimeng Tech · Gate Drive ICs · HTSSOP-28-EP
MS8844 from Hangzhou Ruimeng Tech, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CP1 | passive | Charge pump external capacitor pin; a 0.01uF 100V capacitor connects between CP1 and CP2. |
| 2 | CP2 | passive | Charge pump external capacitor pin; a 0.01uF 100V capacitor connects between CP1 and CP2. |
| 3 | VCP | passive | High-side gate drive voltage from the charge pump; a 0.1uF 16V capacitor is connected to VM per the application figure. |
| 4 | VM | power_in | Power supply voltage, operating range 8V to 36V (absolute maximum -0.3 to 40V). |
| 5 | OUT1 | output | Half-bridge output 1. |
| 6 | SCR12 | passive | Low-side NMOS source of OUT1 and OUT2; a sense resistor can be connected here to set the overcurrent protection. |
| 7 | OUT2 | output | Half-bridge output 2. |
| 8 | OUT3 | output | Half-bridge output 3. |
| 9 | SCR34 | passive | Low-side NMOS source of OUT3 and OUT4 (datasheet text says OUT1, OUT2); a sense resistor can be connected here to set the overcurrent protection. |
| 10 | OUT4 | output | Half-bridge output 4. |
| 11 | VM | power_in | Power supply voltage, operating range 8V to 36V (absolute maximum -0.3 to 40V). |
| 12 | NC | unconnected | Not connected, left floating. |
| 13 | NC | unconnected | Not connected, left floating. |
| 14 | VNEG | power_in | Ground pin or negative supply of a dual-supply arrangement; PGND voltage limit is ±600mV. |
| 15 | V3P3OUT | power_out | Internal 3.3V LDO output supplying up to 10mA, which stays active in sleep mode. |
| 16 | nRESET | input | Reset input, active low; resets the chip, disables all outputs and ignores inputs while low. |
| 17 | nSLEEP | input | Sleep input, active low; enters low-power sleep mode with outputs and charge pump off and internal logic reset, with about 1ms wake-up time. |
| 18 | nFAULT | output | Open-drain fault status output pulled low on overcurrent, overtemperature or undervoltage, with VOL max 500mV at 5mA. |
| 19 | LGND | power_in | Logic input ground, voltage range from VGND to VM-8V. |
| 20 | EN4 | input | Channel 4 enable input; low sets OUT4 to high impedance. |
| 21 | IN4 | input | Channel 4 data input controlling the state of OUT4. |
| 22 | EN3 | input | Channel 3 enable input; low sets OUT3 to high impedance. |
| 23 | IN3 | input | Channel 3 data input controlling the state of OUT3. |
| 24 | EN2 | input | Channel 2 enable input; low sets OUT2 to high impedance. |
| 25 | IN2 | input | Channel 2 data input controlling the state of OUT2. |
| 26 | EN1 | input | Channel 1 enable input; low sets OUT1 to high impedance. |
| 27 | IN1 | input | Channel 1 data input controlling OUT1 (pin table labels it channel 2 data, apparently a typo). |
| 28 | VNEG | power_in | Ground pin or negative supply of a dual-supply arrangement; PGND voltage limit is ±600mV. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Hangzhou Ruimeng Tech |
| Package | HTSSOP-28-EP |
| Category | Power Management ICs |
| Pins | 29 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VM | -0.3 | 40 | V | 3 | ||
| Digital port voltage range | VDin | -0.5 | 7 | V | 3 | ||
| Comparator input voltage range | VCin | -0.5 | 7 | V | 3 | ||
| Pin voltage PGND1,PGND2,PGND3 | VPGND | -600 | 600 | mV | 3 | ||
| Operating temperature | TA | -40 | 150 | ℃ | 3 | ||
| Storage temperature | Tstg | -60 | 150 | ℃ | 3 | ||
| Continuous output current | Icon | 1.75 | A | 3 | |||
| ENx high to OUTx high delay | t1 | 130 | 330 | ns | VM=24V, RL=20Ω, TA=25℃, INx=1 | 3 | |
| ENx low to OUTx low delay | t2 | 275 | 475 | ns | VM=24V, RL=20Ω, TA=25℃, INx=1 | 3 | |
| ENx high to OUTx low delay | t3 | 100 | 300 | ns | VM=24V, RL=20Ω, TA=25℃, INx=0 | 3 | |
| ENx low to OUTx high delay | t4 | 200 | 400 | ns | VM=24V, RL=20Ω, TA=25℃, INx=0 | 3 | |
| INx high to OUTx high delay | t5 | 300 | 500 | ns | VM=24V, RL=20Ω, TA=25℃ | 3 | |
| INx low to OUTx low delay | t6 | 275 | 475 | ns | VM=24V, RL=20Ω, TA=25℃ | 3 | |
| Output rise time | t7 | 30 | 150 | ns | VM=24V, RL=20Ω, TA=25℃ | 3 | |
| Output fall time | t8 | 30 | 150 | ns | VM=24V, RL=20Ω, TA=25℃ | 3 | |
| Supply voltage range | VM | 8 | 36 | V | 4 | ||
| Drive ground voltage | VGNDX | -500 | 500 | mV | 4 | ||
| Internal LDO drive current | ILDO | 0 | 10 | mA | 4 | ||
| Internal LDO output voltage | V3P3 | 3.1 | 3.52 | V | Iout=0 to 10mA | 4 | |
| Operating current | IVM | 1 | 5 | mA | VM=24V, fPWM<50KHz | 4 | |
| Sleep mode current | IVMQ | 450 | 800 | uA | VM=24V | 4 | |
| Undervoltage protection voltage | VUVLO | 6.3 | 8 | V | 4 | ||
| Logic input high level | VIH | 2.2 | 5.25 | V | 4 | ||
| Logic input low level | VIL | 0.6 | 0.7 | V | 4 | ||
| Hysteresis window | VHYS | 50 | 600 | mV | VDD=2.7～3.6V | 4 | |
| Logic input low current | IIL | -5 | 5 | uA | VIN=0 | 4 | |
| Logic input high current | IIH | 100 | uA | VIN=3.3V | 4 | ||
| Pull-down resistance | RPD | 80 | KΩ | 4 | |||
| nFAULT output low voltage | VOL | 500 | mV | IO=5mA | 4 | ||
| nFAULT output high current | IOH | 1 | uA | VO=3.3V | 4 | ||
| High-side FET on-resistance | Rdson | 0.24 | Ω | VM=24V, IO=1A, Tj=25℃ | 4 | ||
| High-side FET on-resistance | Rdson | 0.29 | 0.39 | Ω | VM=24V, IO=1A, Tj=85℃ | 4 | |
| Low-side FET on-resistance | Rdson | 0.24 | 0.39 | Ω | VM=24V, IO=1A, Tj=25℃ | 4 | |
| Off-state leakage current | IOFF | -2 | 2 | uA | 4 | ||
| Dead time | tDEAD | 100 | ns | 4 | |||
| Overcurrent protection | IOCP | 3 | A | 4 | |||
| Overcurrent detection time | tOCP | 6 | us | 4 | |||
| Thermal shutdown | TTSD | 150 | 160 | 180 | ℃ | 4 |
CAD (KiCad official)
- Symbol:
MS8844 - Footprint:
Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm - 3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
- 3D model files:
ms8844-etched.step/ms8844-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ms8844.step/ms8844.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Hangzhou Ruimeng Tech datasheet (12 pp, sha256
ff2fd456766b7589, retrieved 2026-10-26, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MS8844
**Hangzhou Ruimeng Tech** · Gate Drive ICs · HTSSOP-28-EP
MS8844 from Hangzhou Ruimeng Tech, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CP1 | passive | Charge pump external capacitor pin; a 0.01uF 100V capacitor connects between CP1 and CP2. |
| 2 | CP2 | passive | Charge pump external capacitor pin; a 0.01uF 100V capacitor connects between CP1 and CP2. |
| 3 | VCP | passive | High-side gate drive voltage from the charge pump; a 0.1uF 16V capacitor is connected to VM per the application figure. |
| 4 | VM | power_in | Power supply voltage, operating range 8V to 36V (absolute maximum -0.3 to 40V). |
| 5 | OUT1 | output | Half-bridge output 1. |
| 6 | SCR12 | passive | Low-side NMOS source of OUT1 and OUT2; a sense resistor can be connected here to set the overcurrent protection. |
| 7 | OUT2 | output | Half-bridge output 2. |
| 8 | OUT3 | output | Half-bridge output 3. |
| 9 | SCR34 | passive | Low-side NMOS source of OUT3 and OUT4 (datasheet text says OUT1, OUT2); a sense resistor can be connected here to set the overcurrent protection. |
| 10 | OUT4 | output | Half-bridge output 4. |
| 11 | VM | power_in | Power supply voltage, operating range 8V to 36V (absolute maximum -0.3 to 40V). |
| 12 | NC | unconnected | Not connected, left floating. |
| 13 | NC | unconnected | Not connected, left floating. |
| 14 | VNEG | power_in | Ground pin or negative supply of a dual-supply arrangement; PGND voltage limit is ±600mV. |
| 15 | V3P3OUT | power_out | Internal 3.3V LDO output supplying up to 10mA, which stays active in sleep mode. |
| 16 | nRESET | input | Reset input, active low; resets the chip, disables all outputs and ignores inputs while low. |
| 17 | nSLEEP | input | Sleep input, active low; enters low-power sleep mode with outputs and charge pump off and internal logic reset, with about 1ms wake-up time. |
| 18 | nFAULT | output | Open-drain fault status output pulled low on overcurrent, overtemperature or undervoltage, with VOL max 500mV at 5mA. |
| 19 | LGND | power_in | Logic input ground, voltage range from VGND to VM-8V. |
| 20 | EN4 | input | Channel 4 enable input; low sets OUT4 to high impedance. |
| 21 | IN4 | input | Channel 4 data input controlling the state of OUT4. |
| 22 | EN3 | input | Channel 3 enable input; low sets OUT3 to high impedance. |
| 23 | IN3 | input | Channel 3 data input controlling the state of OUT3. |
| 24 | EN2 | input | Channel 2 enable input; low sets OUT2 to high impedance. |
| 25 | IN2 | input | Channel 2 data input controlling the state of OUT2. |
| 26 | EN1 | input | Channel 1 enable input; low sets OUT1 to high impedance. |
| 27 | IN1 | input | Channel 1 data input controlling OUT1 (pin table labels it channel 2 data, apparently a typo). |
| 28 | VNEG | power_in | Ground pin or negative supply of a dual-supply arrangement; PGND voltage limit is ±600mV. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Hangzhou Ruimeng Tech |
| Package | HTSSOP-28-EP |
| Category | Power Management ICs |
| Pins | 29 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VM | -0.3 | | 40 | V | | 3 |
| Digital port voltage range | VDin | -0.5 | | 7 | V | | 3 |
| Comparator input voltage range | VCin | -0.5 | | 7 | V | | 3 |
| Pin voltage PGND1,PGND2,PGND3 | VPGND | -600 | | 600 | mV | | 3 |
| Operating temperature | TA | -40 | | 150 | ℃ | | 3 |
| Storage temperature | Tstg | -60 | | 150 | ℃ | | 3 |
| Continuous output current | Icon | | | 1.75 | A | | 3 |
| ENx high to OUTx high delay | t1 | 130 | | 330 | ns | VM=24V, RL=20Ω, TA=25℃, INx=1 | 3 |
| ENx low to OUTx low delay | t2 | 275 | | 475 | ns | VM=24V, RL=20Ω, TA=25℃, INx=1 | 3 |
| ENx high to OUTx low delay | t3 | 100 | | 300 | ns | VM=24V, RL=20Ω, TA=25℃, INx=0 | 3 |
| ENx low to OUTx high delay | t4 | 200 | | 400 | ns | VM=24V, RL=20Ω, TA=25℃, INx=0 | 3 |
| INx high to OUTx high delay | t5 | 300 | | 500 | ns | VM=24V, RL=20Ω, TA=25℃ | 3 |
| INx low to OUTx low delay | t6 | 275 | | 475 | ns | VM=24V, RL=20Ω, TA=25℃ | 3 |
| Output rise time | t7 | 30 | | 150 | ns | VM=24V, RL=20Ω, TA=25℃ | 3 |
| Output fall time | t8 | 30 | | 150 | ns | VM=24V, RL=20Ω, TA=25℃ | 3 |
| Supply voltage range | VM | 8 | | 36 | V | | 4 |
| Drive ground voltage | VGNDX | -500 | | 500 | mV | | 4 |
| Internal LDO drive current | ILDO | 0 | | 10 | mA | | 4 |
| Internal LDO output voltage | V3P3 | 3.1 | | 3.52 | V | Iout=0 to 10mA | 4 |
| Operating current | IVM | | 1 | 5 | mA | VM=24V, fPWM<50KHz | 4 |
| Sleep mode current | IVMQ | | 450 | 800 | uA | VM=24V | 4 |
| Undervoltage protection voltage | VUVLO | 6.3 | | 8 | V | | 4 |
| Logic input high level | VIH | 2.2 | | 5.25 | V | | 4 |
| Logic input low level | VIL | | 0.6 | 0.7 | V | | 4 |
| Hysteresis window | VHYS | 50 | | 600 | mV | VDD=2.7～3.6V | 4 |
| Logic input low current | IIL | -5 | | 5 | uA | VIN=0 | 4 |
| Logic input high current | IIH | | | 100 | uA | VIN=3.3V | 4 |
| Pull-down resistance | RPD | | 80 | | KΩ | | 4 |
| nFAULT output low voltage | VOL | | | 500 | mV | IO=5mA | 4 |
| nFAULT output high current | IOH | | | 1 | uA | VO=3.3V | 4 |
| High-side FET on-resistance | Rdson | | 0.24 | | Ω | VM=24V, IO=1A, Tj=25℃ | 4 |
| High-side FET on-resistance | Rdson | | 0.29 | 0.39 | Ω | VM=24V, IO=1A, Tj=85℃ | 4 |
| Low-side FET on-resistance | Rdson | | 0.24 | 0.39 | Ω | VM=24V, IO=1A, Tj=25℃ | 4 |
| Off-state leakage current | IOFF | -2 | | 2 | uA | | 4 |
| Dead time | tDEAD | | 100 | | ns | | 4 |
| Overcurrent protection | IOCP | 3 | | | A | | 4 |
| Overcurrent detection time | tOCP | | 6 | | us | | 4 |
| Thermal shutdown | TTSD | 150 | 160 | 180 | ℃ | | 4 |
## CAD (KiCad official)
- Symbol: `MS8844`
- Footprint: `Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm`
- 3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
- 3D model files: `ms8844-etched.step` / `ms8844-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ms8844.step` / `ms8844.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Hangzhou Ruimeng Tech datasheet](docs/ms8844-datasheet.pdf) (12 pp, sha256 `ff2fd456766b7589`, retrieved 2026-10-26, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ms8844-datasheet.pdf)