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MS5620

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Hangzhou Ruimeng Tech Digital To Analog Converters (DAC), SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MS5620

Hangzhou Ruimeng Tech · Digital To Analog Converters (DAC) · SOP-14

MS5620 from Hangzhou Ruimeng Tech, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Reference ground potential for the device; the DAC output of 0 V (zero code) is referenced to this pin.
2 REFA input Reference voltage input for DAC channel A, which has high input impedance; the absolute input range is -0.3 V to VDD+0.3 V.
3 REFB input Reference voltage input for DAC channel B, which has high input impedance; the absolute input range is -0.3 V to VDD+0.3 V.
4 REFC input Reference voltage input for DAC channel C, which has high input impedance; the absolute input range is -0.3 V to VDD+0.3 V.
5 REFD input Reference voltage input for DAC channel D, which has high input impedance; the absolute input range is -0.3 V to VDD+0.3 V.
6 DATA input Serial interface digital data input; each bit is written into the serial register on the falling edge of CLK, with digital inputs limited to -0.3 V to VDD+0.3 V.
7 CLK input Serial interface clock; input data is written into the serial register on the falling edge of CLK, with a maximum clock frequency of 1 MHz.
8 LOAD input Serial interface data load; when LDAC is low, a falling edge on LOAD latches data into the output latch and immediately converts it on the selected DAC channel.
9 DACD output Analog voltage output of DAC channel D, buffered with a selectable gain of 1 or 2 times the reference voltage.
10 DACC output Analog voltage output of DAC channel C, buffered with a selectable gain of 1 or 2 times the reference voltage.
11 DACB output Analog voltage output of DAC channel B, buffered with a selectable gain of 1 or 2 times the reference voltage.
12 DACA output Analog voltage output of DAC channel A, buffered with a selectable gain of 1 or 2 times the reference voltage.
13 LDAC input DAC data load; when high, the DAC outputs are not updated while data is shifted in, and the outputs update only on a high-to-low transition of LDAC.
14 VDD power_in Power supply voltage; recommended operation is 2.7 V to 5.25 V, with an absolute maximum of 7 V.

Key specifications

Parameter Value
Manufacturer Hangzhou Ruimeng Tech
Package SOP-14
Category Data Acquisition
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
电源电压 VDD 2.7 5.25 V 4
最小输入电压 (VIL) VIL 0.8 V 4
工作温度范围 -40 85 °C 4
供电电压 VDD 7 V 4
数字输入电压范围 -0.3 V 4
基准输入电压范围 VID -0.3 V 4
工作温度 TA -40 85 C 4
存储温度 Tstg -50 150 C 4
引线焊接温度 260 C 1.6mm 引线持续 10 秒 4
高电平输入电流 IIH IIH -10 10 μA VDD=3.3V±5%; VI=VDD 4
低电平输入电流 IIL IIL -10 10 μA VDD=3.3V±5%; VI=0 4
输入基准电流 Iref Iref -10 10 μA VDD=3.3V; VREF=1.5V 4
末端线性误差 EL -1 1 LSB VREF=1.25V; Gain=2 4
微分线性误差 ED -0.9 0.9 LSB VREF=1.25V 4
零点误差 EZS 0 30 mV VREF=1.25V; Gain=2 5
满刻度误差 EFS -60 60 mV VREF=1.25V; Gain=2 5
满刻度温度系数 -25 25 μV/℃ VREF=1.25V; Gain=2 5
高电平输入电流 IIH IIH -10 10 μA VDD=5V±5%; VI=VDD 5
低电平输入电流 IIL IIL -10 10 μA VDD=5V±5%; VI=0 5
输入基准电流 Iref Iref -10 10 μA VDD=5V; VREF=2V 5
末端线性误差 EL -1 1 LSB VREF=2V; Gain=2 5
微分线性误差 ED -0.9 0.9 LSB VREF=2V; Gain=2 5
电流沉输出 IO(sink) IO(sink) 20 μA VDD=3.3V±5%; Each DAC Output 4
电流源输出 IO(source) IO(source) 1 mA VDD=3.3V±5%; Each DAC Output 4
电流沉输出 IO(sink) IO(sink) 20 μA VDD=5V±5%; Each DAC Output 5
电流源输出 IO(source) IO(source) 2 mA VDD=5V±5%; Each DAC Output 5
输入电容 Ci 15 pF 4
输入参考电容 15 pF 4
电源电流 IDD IDD 2 mA VDD=3.3V 4
电源电流 IDD IDD 2 mA VDD=5V 5
零点误差温度系数 10 μV/℃ VREF=1.25V; Gain=2 5
电源灵敏度 PSRR PSRR 0.5 mV/V 5
输出压摆率 1 V/μs CL = 100 pF, RL = 10 kΩ 11
输出建立时间 10 μs 到±0.5LSB 以内，CL = 100 pF, RL = 10 kΩ 11
大信号带宽 100 kHz -3dB 点测试 11
数字串扰 -50 dB CLK=1MHz 的方波在 DACA-DACD 点测试 11
参考电压馈通 -60 dB 见注 10 11
通道隔离度 -60 dB 见注 11 11
参考电压输入带宽 100 kHz 见注 12 11
CLK 频率 1 MHz 8
建立时间，数据输入 tsu(DATA-CLK) 50 ns 见图 1 和图 2 8
有效时间，数据输入有效在 CLK↓后 tv(CLK_LOAD) 50 ns 见图 1 和图 2 8
建立时间，CLK 下降沿到 LOAD tsu(CLK-LOAD) 50 ns 见图 1 8
建立时间，LOAD↑到 CLK↓ tsu(LOAD-CLK) 50 ns 见图 1 8
脉冲宽度，LOAD tw(LOAD) 250 ns 见图 1 8
脉冲宽度，LDAC tw(LDAC) 250 ns 见图 2 8
建立时间，LOAD↑到 LDAC↓ tsu(LOAD-LDAC) 0 ns 见图 2 9

CAD (KiCad official)

  • Symbol: MS5620
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: ms5620-etched.step / ms5620-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ms5620.step / ms5620.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Hangzhou Ruimeng Tech datasheet (17 pp, sha256 514bf752edf059d8, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF